Makefile include list of object files recursively - c

Question

I haven been working with the Linux kernel for some time now and I am interested in adapting the Makefile structures used there. I want to achieve something similar by creating a set of Makefiles in each subdirectory which only consists the names of the files I really want to compile when building my project. A typical similar example achieved in the Linux kernel looks like this:
obj-y += file1.o
obj-y += file2.o
obj-y += file3.o
obj-y += file4.o
# ...
obj-d += somesubdir
Now, when building my project, I use the Makefile in my root directory to recursively include each Makefile in the individual subdirectories and append it to the list of the obj-y variable. My current approach is to define a recursive function which handles including the Makefiles and iterate through each subdirectory automatically:
OBJS :=
objtree := .
srctree := .
# ...
define build_subdir
objtree := $$(objtree)/$(1)
srctree := $$(srctree)/$(1)
obj-y :=
obj-d :=
include $$(srctree)/Makefile
OBJS += $$(patsubst %,$$(objtree)/%,$$(obj-y))
$$(foreach subdir,$$(obj-d),$$(eval $$(call build_subdir,$$(subdir))))
srctree := $$(patsubst %/$(1),%,$$(srctree))
objtree := $$(patsubst %/$(1),%,$$(objtree))
endef
# ...
$(eval $(call build_subdir,src))
$(eval $(call build_subdir,src/subdir))
While iterating through all subdirectories, I add the individual files to the OBJS variable which is then later used to compile the file.
However, the OBJS variable only contains the name of the object file (i.e. the target), not the name of the actual source file. This is problematic since the source files in my project do not consist only of .c but also some assembly files (.S). Therefore I am not able to define a recipe which looks like this:
define compile_file
$(1): $$(patsubst %.o,%.c,$(1))
$(CC) $< -o $# $(CFLAGS)
endef
In my case, the compiler is always the same, so there's no problem in keeping the $(CC) variable as is. The same goes for the $(CFLAGS) variable.
Is there a way to achieve this similarily to the Linux kernel?
This is the current relevant content of my Makefile:
objtree := .
srctree := .
.PHONY: all
all: real-all
OBJS :=
define build_subdir
objtree := $$(objtree)/$(1)
srctree := $$(srctree)/$(1)
obj-y :=
obj-d :=
include $$(srctree)/Makefile
OBJS += $$(patsubst %,$$(objtree)/%,$$(obj-y))
$$(foreach subdir,$$(obj-d),$$(eval $$(call build_subdir,$$(subdir))))
srctree := $$(patsubst %/$(1),%,$$(srctree))
objtree := $$(patsubst %/$(1),%,$$(objtree))
endef
# $(eval $(call build_subdir, src))
$(eval $(call build_subdir,src/arch/$(ARCH)))
define compile_file
$(1): $$(patsubst %.o,%.S,$(1))
#echo "Compiling file $$< to file $$#"
endef
$(foreach file,$(OBJS),$(eval $(call compile_file,$(file))))
.PHONY: real-all
real-all: $(OBJS)
#echo "real-all"
And the current output:
Compiling file src/arch/x86/a20.S to file src/arch/x86/a20.o
make: *** No rule to make target 'src/arch/x86/acpi.S', needed by 'src/arch/x86/acpi.o'. Stop.
The last line obviously fails because there's no src/arch/x86/acpi.S file. Instead, the actual file is src/arch/x86/acpi.c. Thats what I addressed before with the issue being the source files can either be a .c or a .S file.

Answer 1

I solved it by using the $(wildcard) function in the following way:
define compile_file
srcbase := $$(basename $(1))
srcfile := $$(wildcard $$(srcbase).*)
$(1): $$(srcfile)
#echo "[ CC ] $$#"
endef
Since $(1) contains the path to the file, srcfile matches the file by looking for the file with $(wildcard $$(basename $(1)).*).
Now, I can compile all files easily.