When I try to list all the contents of a directory (to use later as a dependency) it gives this error at the end of the listing (my permissions are not the problem):
gmake: execvp: filename: Permission denied
gmake: *[test] Error 127
I don't quite understand this, the file is the first in the directory and is fine until the end of the listing, this does list all the files. I ran gmake -n to see if its trying to execute and it does not for this target. Sorry if I speak incorrectly, this is my first try at a complex make file.
Here is my code:
test:
$(wildcard $(MY_DIR)/*.cpp)
Thanks.
Now I have to find out what's going on. Time for some more experiments. With one .cpp file in the working directory, call it foo.cpp, and this makefile:
SRC := $(wildcard *.cpp)
$(info SRC is $(SRC))
test1: foo.cpp
#echo $# sees $^
try make, and tell us the result.
Related
I am trying to create a directory at rootpath, e.g. /my_own_dir/.
Here's what I do:
struct file *fp = filp_open("/my_own_dir/",O_DIRECTORY|O_CREAT, 0755);
The .ko can be compiled. However, when I insmod .ko the terminal just froze.
Neither was the directory created nor the mod seemed to be inserted.
So my question is, is it possible to create such a directory? If so, what's wrong with my method?
I'm using a Ubuntu 18.04 with Kernel version 5.11.0.
My solution is to symlink the source files into the bin directory and dynamically generate a new MakeFile in the bin directory. This allows all build files to be cleaned up easily since the dynamic Makefile can always just be recreated.
INCLUDE=include
SOURCE=src
TARGET=mymodule
OUTPUT=bin
EXPORT=package
SOURCES=$(wildcard $(SOURCE)/*.c)
# Depends on bin/include bin/*.c and bin/Makefile
all: $(OUTPUT)/$(INCLUDE) $(subst $(SOURCE),$(OUTPUT),$(SOURCES)) $(OUTPUT)/Makefile
make -C /lib/modules/$(shell uname -r)/build M=$(PWD)/$(OUTPUT) modules
# Create a symlink from src to bin
$(OUTPUT)/%: $(SOURCE)/%
ln -s ../$< $#
# Generate a Makefile with the needed obj-m and mymodule-objs set
$(OUTPUT)/Makefile:
echo "obj-m += $(TARGET).o\n$(TARGET)-objs := $(subst $(TARGET).o,, $(subst .c,.o,$(subst $(SOURCE)/,,$(SOURCES))))" > $#
clean:
rm -rf $(OUTPUT)
mkdir $(OUTPUT)
If you are building inside the kernel tree you can use the O variable:
make O=/path/to/mydir
If you are compiling outside the kernel tree (module, or any other kind of program) you need to change your Makefile to output in a different directory. Here a little example of a Makefile rule which output in the MY_DIR directory:
$(MY_DIR)/test: test.c
gcc -o $# $<
and then write:
$ make MY_DIR=/path/to/build/directory
Or a workaround:
Create a sub-directory with/for every arch name (e.g. "debug_64").
Under "debug_64": create symbolic link of all .c and .h files. Keeping the same structure.
Copy the makefile to "debug_64" and set the right flags for 64 Debug build, e.g.
ccflags-y := -DCRONO_DEBUG_ENABLED
ccflags-y += -I$(src)/../../../lib/include
KBUILD_AFLAGS += -march=x86_64
Remember to set the relative directories paths to one level down, e.g. ../inc will be ../../inc.
Repeat the same for every arch/profile. Now we have one source code, different folders, and different make files. By the way, creating profiles inside make files for kernel module build is not an easy job, so, I preferred to create a copy of makefile for every arch.
I wrote my own openwrt package for my script and the compilation stage I put it in the package file as this path openwrt / feeds / package / is that the path is correct or not?
or if I have is for the compilation error:
make[1]: *** No rule to make target `package/test/compile'. Stop.
make: *** [package/test/compile] Error 2
THis my Makefile:
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=test
PKG_VERSION:=1.0
PKG_RELEASE:=1
PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)
DEPENDS:= +nmap +python
include $(INCLUDE_DIR)/package.mk
define Package/test
SECTION:=secure
CATEGORY:=Monitoring
TITLE:=test
define Package/test/description
test tis is my first package
endef
define Build/Prepare
mkdir -p $(PKG_BUILD_DIR)
$(CP) ./src/* $(PKG_BUILD_DIR)/
endef
define Package/test/install
$(INSTALL_DIR) $(1)/bin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/test $(1)/bin/
endef
$(eval $(call BuildPackage,test))
I need help please.
thanks.
You don't really have to put your source code anywhere in the /openwrt/ folder. It can be placed, let's say, in /Documents/[name] folder. However it is important that you put your OpenWRT-specific Makefile in the /openwrt/ tree. I am not sure if putting your Makefile in /openwrt/feeds/package is correct but I put my Makefiles in /openwrt/package/[name] folder which works fine. Your source code will be automatically copied by the toolchain to the same folder anyway.
Note: if you place your source code somewhere on your system (for example, in the Documents folder) you have to specify the path to it in your Makefile as follows: PKG_SOURCE_URL:=file://$(TOPDIR)/../Documents/[name]
Your make[1] errors are basically telling you that the toolchain could not find the Makefile. Try putting Makefile in /openwrt/package/[name].
I have a problem that is causing me a headache, it is assumed that the command-L searches the libraries in the current directory of the Makefile, but it's not working for me, for example I have the following command in my Makefile:
...
LDLIBS = -L/libs -lmatrix
main: main.o operations.o display.o
$(CC) $(LDLIBS) $^ -o $#
...
And when I try to compile it literally says:
gcc -L/libs -lmatrix main.o operations.o display.o -o main
/usr/bin/ld: cannot find -lmatrix
collect2: ld returned 1 exit status
make: *** [main] Error 1
But when I simply change "-L/libs" for "-L$(PWD)/libs" it compiles perfectly and my program works fine...
But using "-L$(PWD)" I get another problem, if the name of any directory has a space It doesn't work again, actually I don't know if this problem is irremediable (using $(PWD) or not), but I still have the doubt that why it doesn't work without the $(PWD) because apparently (seeing A LOT of examples on the internet) using -L, the $(PWD) shouldn't be needed.
You're wrong that it's not needed. The path /libs means the libs directory at the root of your filesystem. Just like /bin doesn't mean "the bin directory under my current directory", so /libs doesn't mean the libs directory under the current directory.
If you want to look in libs in the current directory, just use -Llibs or if you want to be more specific, -L./libs (the directory . is the current directory, so cd . changes to the current directory, just like cd .. changes to the parent directory).
The path /PATHNAME means the directory at the root of your filesystem. If you want to use $(PWD) for your current directory then you can quote the shell variables like: "$(PWD)". Do not escape the quotes.
So I've got the following folder structure
makefile
src/my_lib.c
src/myhead.h
and I'm trying to compile *my_lib.c* with the header myhead.h as a library. This is the makefile. I attempt to put the obj files in OBJFOLDER and the compiled library in the OUTPUTFOLDER
PLUGNAME=my_lib
SOURCEFOLDER=src
OUTPUTFOLDER=bin
OBJFOLDER=bin/obj
OBJS=$(PLUGNAME).o
DEPS=myhead.h
# Configuration finishes here
_OBJS = $(patsubst %,$(OBJFOLDER)/%,$(OBJS))
_DEPS = $(patsubst %,$(SOURCEFOLDER)/%,$(DEPS))
ifeq ($(OS),Windows_NT)
EXT = .dll
else
UNAME_S := $(shell uname -s)
ifeq ($(UNAME_S),Linux)
EXT = .so
endif
endif
all : $(OUTPUTFOLDER)/$(PLUGNAME)$(EXT)
$(OUTPUTFOLDER)/$(PLUGNAME)$(EXT) : $(_OBJS)
gcc -Wl,--add-stdcall-alias -shared -o $# $(_OBJS)
$(OBJFOLDER)/%.o: $(SOURCEFOLDER)/%.c $(_DEPS)
mkdir -p $(OUTPUTFOLDER)
mkdir -p $(OBJFOLDER)
gcc $(foreach d, $(INC), -I$d) -c $< -o $#
.PHONY: clean
clean :
rm -f $(OBJFOLDER)/*.o $(OUTPUTFOLDER)/$(PLUGNAME)$(EXT) $(SOURCEFOLDER)/TSDRPlugin.h
When I do make all it fails
make: *** No rule to make target `bin/obj/my_lib.o', needed by `bin/
my_lib.dll'. Stop.
I have no idea how this could be possible since I already have defined
$(OBJFOLDER)/%.o: $(SOURCEFOLDER)/%.c $(_DEPS)
Strangely if I change the above line in the makefile, to
bin/obj/my_lib.o: $(SOURCEFOLDER)/%.c $(_DEPS)
I now get
make: *** No rule to make target `src/%.c', needed by `bin/obj/my_lib.o'. Stop.
Your second error is because by removing the % in the target you've turned this into an explicit rule, not a pattern rule. So, the % in the prerequisite is not replaced.
Your first error means that for some reason make is deciding that your pattern rule doesn't match. This means, usually, that make can't find and doesn't know how to create one of the prerequisites. I recommend you run make with the -d flag and see why make decides your rule doesn't apply.
What version of GNU make are you using? Some very old versions would not match pattern rules if the directory that the target was to be placed into didn't exist already.
The problem was that header was missing... Stupid mistake on my side.
I overlooked it, because this was a snippet from a longer makefile that was supposed to copy over the header but it didn't which means that this line was outputting the error. Stupid me...
I have the strangest problem.
when I run : make tests
in the console I get the following error:
gcc: album_test.o: No such file or directory
sorry for attaching the content as a pic,
the site kept giving me a: "Your post appears to contain code that's not properly formatted
as code"
when I change this line :
album_test.o: ./tests/album_test.c album.h
to be :
album_test.o: album_test.c album.h
and place the album_test.c in the same directory as the makefile
everything compiles!
It's very important that the file will be in a separate tests directory.
any ideas?
Thanks!
You're trying to use make's built-in implicit rules to build your object files. That works when make can find the source file in the current directory, but not otherwise. Update this rule:
album_test.o: ./tests/album_test.c album.h
To include a recipe:
album_test.o: ./tests/album_test.c album.h
$(CC) $(CFLAGS) -c -o $# $<