Why is this Makefile wrong? Linker fails only if preceded by compiler error - c

Question

This is the example program to make it easier to explain. Have this 4 files, main.c, sum.c and header.h. and finally the Makefile.
main.c
#include <stdio.h>
#include "header.h"
int main()
{
int a = 1;
int b = 1;
int c = sum(a, b);
printf("Sum: %i\n",c);
return (0);
}
sum.c
#include "header.h"
int sum(int a, int b)
{
return (a + b);
}
header.h
int sum(int a, int b);
Makefile
TEST_SRCS = *.c
TEST_OBJS = $(TEST_SRCS:%.c=%.o)
%.o : %.c *.h
gcc -c $^
assemble_test: $(TEST_OBJS);
test: assemble_test
gcc -o test *.o
./test
clean:
#rm -rf *.o *.gch test
#echo "Cleaned"
Steps to reproduce:
Call test rule: make test > all ok.
Introduce any error on purpose, example two commas:
printf("Sum: %i\n",,c);
Call test rule: make test > Getting normal syntax error.
Remove the error. Save file.
Call test rule: make test > Getting linker error no matter what.
gcc -o test *.o
Undefined symbols for architecture x86_64:
"_main", referenced from:
implicit entry/start for main executable
ld: symbol(s) not found for architecture x86_64
clang: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [test] Error 1
Use clean rule to start again every time.
Have this behaviuor for a while and i cant figure the problem. To be honest im new to Makefiles so i must be doing something very wrong.
About the test rule calling assemble_test. Its because part of a larger Makefile and i need diferent rules for diferent purposes to compile the objects, so dont mind.
Can you please help me understand what is going on?
Thanks.

Answer 1

It's wrong to use wildcards for the object files. Wildcards match files that already exist on the disk when make runs. That doesn't help because obviously they won't match files that do not yet exist, and the entire point of your makefile is to create files that don't exist.
So this:
TEST_SRCS = *.c
TEST_OBJS = $(TEST_SRCS:%.c=%.o)
leaves the value of TEST_SRCS the string *.c and the value of TEST_OBJS the string *.o (perhaps you were thinking that wildcards are expanded immediately, somehow? No, that's not the case).
Then this line:
assemble_test: $(TEST_OBJS);
causes the target assemble_test to list *.o as a prerequisite: this will be expanded to all the object files that already exist in the directory. But of course it won't expand to object files that you want make to create, but don't exist yet.
There are lots of other problems here: for example you don't want to compile $^ because that expands to all the prerequisites but you only want to compile source files, not header files. And the addition of assemble_test seems odd and makes things harder.
You probably want this, assuming you're using GNU make:
TEST_SRCS := $(wildcard *.c )
TEST_OBJS = $(TEST_SRCS:%.c=%.o)
%.o : %.c *.h
gcc -c $<
test: $(TEST_OBJS)
gcc -o $# $^
./$#
By using the wildcard function you expand the value of the sources glob first before you replace the results with .o.