A1_SRC and A2_SRC define the source C codes that I would compile. A1_SRC and A2_SRC share the same headers const.h and var.h. I attach my Makefile below:
EXEC=../bin
OBJ=../obj
CC=mpicc
CFLAGS=-O3 -Wall -traceback
LFLAGS=-lm -lfftw3 -lstdc++ -lmpi
$(OBJ)/%.o: %.c
$(CC) -c $(CFLAGS) $< -o $#
$(CC) $(CFLAGS) -MM $*.c > $(OBJ)/$*.d
A1_OBJ = $(A1_SRC:%.c=$(OBJ)/%.o)
A2_OBJ = $(A2_SRC:%.c=$(OBJ)/%.o)
A1_SRC = \
test.c \
alloc.c \
func.c
A2_SRC = \
test1.c \
test2.c
A1: $(A1_OBJ) const.h var.h
$(CC) $(LFLAGS) $(A1_OBJ) -o $(EXEC)/test_A1
A2: $(A2_OBJ) const.h var.h
$(CC) $(LFLAGS) $(A2_OBJ) -o $(EXEC)/test_A2
all: A1 A2
.PHONY: clean
clean:
rm -f $(OBJ)/*.o $(OBJ)/*.d $(EXEC)/*
install: clean all
-include $(A1_OBJ:$(OBJ)/.o=$(OBJ)/.d) $(A2_OBJ:$(OBJ)/.o=$(OBJ)/.d)
Traditionally, in a simple way, we define a pattern rule to compile .o files from .c codes. In this Makefile,
$(CC) -c $(CFLAGS) $< -o $#, A1_OBJ = $(A1_SRC:%.c=$(OBJ)/%.o), A2_OBJ = $(A2_SRC:%.c=$(OBJ)/%.o)
can realize this goal. The next step is to perform linking to generate executable file, which is realized by
$(CC) $(LFLAGS) $(A1_OBJ) -o $(EXEC)/test_A1, $(CC) $(LFLAGS) $(A2_OBJ) -o $(EXEC)/test_A2
However, I don't understand why it also compiles the so-called dependency files using $(CC) $(CFLAGS) -MM $*.c > $(OBJ)/$*.d? And then the Makefile does not use these .d files until the last line -include $(A1_OBJ:$(OBJ)/.o=$(OBJ)/.d) $(A2_OBJ:$(OBJ)/.o=$(OBJ)/.d)... What does the last line mean and how it is related to the .o files?
Also, in this pattern rule:
A1: $(A1_OBJ) const.h var.h
$(CC) $(LFLAGS) $(A1_OBJ) -o $(EXEC)/test_A1
why do we need two lines? I can't figure out why we should put the first line $(A1_OBJ) const.h var.h here?
I expect experienced programmer could help answer my questions. It would help more people who have the same doubt as me find a solution.
Related
I'm trying to understand if I have create the Makefile right. I have the following files:
Student.h Student.C University.h University.c list.h IDCard.h IDCard.c union.h
Also I have a library mylib which I use the list.h and union.h from.
Furthermore, I have the following hierarchy:
- University
- Student
- list
- IDCard
- union
This means that University imports Student and union and Student import list and IDCard.
The steps I need to follow:
Use the make command to create testing1.exe - release mode without asserts. This file is the runnable of the given testing1.c.
Use make testing2.exe for creating test2.exe - release mode without asserts. This file is the runable of testing2.c.
Use make testing2_debug.exe for creating testing2_debug.exe - debug mode, with asserts. This file is the runable of test2.c.
Use make test for creating test.exe - release mode without asserts. This file is runnable of test.c.
Use make clean to clean so the rebuild will succeed.
The Makefile I wrote looks like:
CC = gcc
OBJS = IDCard.o Student.o University.o
DEBUG_OBJS = IDCard_debug.o Student_debug.o University_debug.o
SOURCE = IDCard.c Student.c University.c
HEADER = IDCard.h Student.h University.h list.h union.h
CFLAGS = -std=c99 -Wall -pedantic-errors -Werror -DNDEBUG -L. -mylib
EXEC = testing.exe testing1.exe testing2.exe testing2_debug.exe
testing_O = testing1.o testing2.o testing2_debug.o testing.o
#make testing1.exe
testing1.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#make testing2.exe
testing2.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#testing2_debug.exe
testing2_debug.exe : $(DEBUG_OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
#make testing.exe
testing.exe : $(OBJS) $*.o
$(CC) -o $# -DNDEBUG $(OBJS) -L. mylib
testing1.o : testing1.c Student.h University.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
Student.o : list.h IDCard.h Student.c Student.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
University.o : union.h University.c University.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
IDCard.o : IDCard.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
testing2_debug.o : testing2.c Student.h University.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
Student_debug.o : list.h IDCard.h Student.c Student.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
University_debug.o : union.h University.c University.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
IDCard_debug.o : IDCard.h
$(CC) -c -g $(CFLAGS) $*.c -o $#
clean :
rm -f $(OBJS) $(DEBUG_OBJS) $(EXEC) $(testing_O)
I'm a bit new to creating Makefiles so I'm try to make as few mistakes as possible. Does my Makefile do what I need? Can it be simplified? Does it follow the conventions?
$*.o shouldn't be a dependency. $(OBJS) already covers that.
As a general rule, you can avoid targets for individual object files.
Here's an example target that may need modification to suit your needs:
%.o: %.c %.h
<tab>$(CC) -DNDEBUG -c $(CFLAGS) -o $# $<
%_debug.o: %.c %.h
<tab>$(CC) -c -g $(CFLAGS) -o $# $<
This requires the header file to have the same base name as the source file.
Another option that may work is listing off the header file dependencies of each object file and then doing the matching:
testing1.o: Student.h University.h
Student.o: list.h IDCard.h Student.h
University.o: union.h University.h
IDCard.o: IDCard.h
testing2_debug.o: Student.h University.h
Student_debug.o: list.h IDCard.h Student.h
University_debug.o: union.h University.h
IDCard_debug.o: IDCard.h
%.o: %.c
<tab>$(CC) -DNDEBUG -c $(CFLAGS) -o $# $<
%_debug.o: %.c
<tab>$(CC) -c -g $(CFLAGS) -o $# $<
A similar rule can be followed for .exe files:
%.exe: $(OBJS)
<tab>$(CC) -DNDEBUG $(CFLAGS) $^ -o $# -L. -lmylib
%_debug.exe: $(DEBUG_OBJS)
<tab>$(CC) -g $(CFLAGS) $^ -o $# -L. -lmylib
Also, make sure to replace <tab> in these examples with hard tabs for your Makefile to be valid.
IDCard.o : IDCard.h
$(CC) -c -DNDEBUG $(CFLAGS) $*.c
but .h files aren't compiled
As a general style form list .c dependencies before .h dependencies.
EDIT: Community Wiki. If it weren't for the clarifying comment by OP I would now delete this post.
Iam working with gcc and MinGW on a Windows platform. I have a directory containing two *.c files:
main.c and funcs.c
I am using the following makefile:
CC=gcc
CFLAGS=-c
LDFLAGS=
SOURCEDIR = src
BUILDDIR = build
SOURCES=$(wildcard $(SOURCEDIR)/*.c)
OBJECTS=$(patsubst $(SOURCEDIR)/%.c,$(BUILDDIR)/%.o,$(SOURCES))
LIBRARIES=-L/mingw64/lib
INC= -I./include
EXECUTABLE=testLink
VPATH = src include build
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) $(LIBRARIES) -o ./dist/$#
$(OBJECTS): $(SOURCES)
$(CC) $(INC) $(CFLAGS) $< -o $#
Which should take the *.c files and generate *.o files with the same name. However I get the following output on make -
$ make
gcc -I./include -c src/funcs.c -o build/funcs.o
gcc -I./include -c src/funcs.c -o build/main.o
gcc build/funcs.o build/main.o -L/mingw64/lib -o ./dist/testLink
followed of course by a bunch of multiple definition errors. As you can see from the first two lines it is taking the same *.c file and compiling it twice into two different *.o files.
I am new to makefiles but I assume it is something wrong with my $(OBJECTS) rule and I'm pretty sure it's the $< which is causing the problem. I'm trying to create a generic makefile which will always work on my projects which have the same directory structure and take .c files turn them into .o files and link. Am I going about this entirely the wrong way or is there a simple fix to my makefile?
Thanks!
James
This rule:
$(OBJECTS): $(SOURCES)
$(CC) $(INC) $(CFLAGS) $< -o $#
expands to:
funcs.o main.c: funcs.c main.c
$(CC) $(INC) $(CFLAGS) $< -o $#
which is equivalent to:
funcs.o: funcs.c main.c
$(CC) $(INC) $(CFLAGS) $< -o $#
main.o: funcs.c main.c
$(CC) $(INC) $(CFLAGS) $< -o $#
$< refers to the first dependency (funcs.c) so your Makefile is trying to generate both funcs.o and main.o from the same source.
You just want a generic rule using % wildcard matching:
%.o: %.c
$(CC) $(INC) $(CFLAGS) $< -o $#
See https://www.gnu.org/software/make/manual/html_node/Pattern-Rules.html
Jeff pointed the mistake in his answer (all objects depend on all sources: that isn't a generic compilation rule for c sources).
However, the generic rule must have source & object paths. To sum it up, just replace
$(OBJECTS): $(SOURCES)
$(CC) $(INC) $(CFLAGS) $< -o $#
by
$(BUILDDIR)/%.o : $(SOURCEDIR)/%.c
$(CC) $(INC) $(CFLAGS) $< -o $#
(as explained in How to generate a Makefile with source in sub-directories using just one makefile)
note that this kind of dependency test doesn't take included .h files into account, so it's only intended for first builds. Modifying .h files afterwards doesn't trigger a compilation since the header files are not listed as dependencies.
Can someone help me understand the below makefile?
I have comment on the bits I am not sure on. I have used make files but not extensively and I do not believe I have followed good practises so any advice is welcome.
CC=gcc #is CC, libs, deps, obj, etc predefined keywords or could I use something else
CFLAGS=-I. -g -D_FILE_OFFSET_BITS=64 -I/usr/include/fuse #same with CFlags
LIBS = -luuid -lfuse -pthread
DEPS = fs.h unqlite.h
OBJ = unqlite.o fs.o
TARGET1 = test
TARGET2 = test2
TARGET3 = test3
TARGET4 = test4
TARGET5 = main
all: $(TARGET1) $(TARGET2) $(TARGET3) $(TARGET4) $(TARGET5)
%.o: %.c $(DEPS) #not sure on this line
$(CC) -c -o $# $< $(CFLAGS) #same here
$(TARGET1): $(TARGET1).o $(OBJ)
gcc -o $# $^ $(CFLAGS) $(LIBS) #what are $# and $^
$(TARGET2): $(TARGET2).o $(OBJ)
gcc -o $# $^ $(CFLAGS) $(LIBS)
$(TARGET3): $(TARGET3).o $(OBJ)
gcc -o $# $^ $(CFLAGS) $(LIBS)
$(TARGET4): $(TARGET4).c
gcc -o test test.c
$(TARGET5): $(TARGET5).c
gcc -o uuid uuid.c -luuid
.PHONY: clean
clean:
rm -f *.o *~ core $(TARGET1) $(TARGET2) $(TARGET3) $(TARGET4) $(TARGET5)
CC, CFLAGS, LIBS, DEPS, OBJ and TARGETs are not predefined keywords. They are variables. You can change the name into any you feel appropriate. Just make sure you also change their reference names: $(CC) $(CFLAGS) etc.
%.o: %.c $(DEPS) -
It is a pattern rule: https://www.gnu.org/software/make/manual/html_node/Pattern-Rules.html
In brief, it says: any .o file depends on .c file with the same prefix and $(DEPS) (which are fs.h and unqlite.h)
$#, $<, $^ are automatic variables for the rules: https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html#Automatic-Variables
If works the following way: when making test.o object file from source, the rule
%.o: %.c $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
Is interpreted as:
test.o: test.c fs.h unqlite.h
gcc -c -o test.o test.c -I. -g -D_FILE_OFFSET_BITS=64 -I/usr/include/fuse
Then, when making test binary, the rule
$(TARGET1): $(TARGET1).o $(OBJ)
gcc -o $# $^ $(CFLAGS) $(LIBS)
Becomes:
test: test.o unqlite.o fs.o
gcc -o test test.o unqlite.o fs.o -I. -g -D_FILE_OFFSET_BITS=64 -I/usr/include/fuse -luuid -lfuse -pthread
So, we can see, CFLAGS reference is useless in the rule, as it defines compilation flags, and the rule actually performs linking. So the right one would be:
$(TARGET1): $(TARGET1).o $(OBJ)
gcc -o $# $^ $(LDFLAGS) $(LIBS)
Where LDFLAGS would be defined to some useful value, or can be left empty:
LDFLAGS =
I'll say first I don't have as much experience which makefiles as I wished, this is actually my first.
The error I currently get is:
Makefile:1: missing separator. Stop.
This happens when I try to run the make command.
As far as I know this means that I'm missing a hard tab at the first line it tries to run, I think at least.
I'm not missing a hard tab though as far as I know, so I'm assuming I'm just missing a whole line somewhere.
CFLAGS = -ansi -Wall -pedantic
HEADERS = menu.h file1.h file2.h file3.h file4.h
OBJECTS = menu.o file1.o file2.o file3.o file4.o
CC = gcc
all:runprog
runprog:$(OBJECTS)
$(CC) $(OBJECTS) -o runprog
menu.o:menu.c $(HEADERS)
$(CC) $(CFLAGS)
file1.o:file1.c $(HEADERS)
$(CC) $(CFLAGS)
file2.o:file2.c $(HEADERS)
$(CC) $(CFLAGS)
file3.o:file3.c $(HEADERS)
$(CC) $(CFLAGS)
file4.o:file4.c $(HEADERS)
$(CC) $(CFLAGS)
clean:rm -f *.o runprog
The clean target has its code in the place of dependencies. Also, your code uses spaces instead of tabs. Additionally, you forgot to add the .c files to the CC command lines. Moreover, you can simplify all the rules to
CFLAGS = -ansi -Wall -pedantic
HEADERS = menu.h file1.h file2.h file3.h file4.h
OBJECTS = menu.o file1.o file2.o file3.o file4.o
CC = gcc
all:runprog
runprog:$(OBJECTS)
$(CC) $(OBJECTS) -o runprog
%.o: %.c $(HEADERS)
$(CC) -c -o $# $< $(CFLAGS)
clean:
rm -f *.o runprog
I need to modify the Makefile I have to store only the object file associated with "record.c" into the bin folder. Here is what my directory structure looks like before executing Make.
bin/
include/
-hash_table.h
-history.h
-parser.h
-record.h
-shell.h
-variables.h
lib/
obj/
src/
-hash_table.c
-history.c
-parser.c
-record.c
-shutil.c
-sshell.c
-variables.c
...and here is the Makefile:
# Beginning of Makefile
SRC = src/shutil.c src/parser.c src/sshell.c src/history.c src/hash_table.c src/variables.c src/record.c
OBJS = obj/shutil.o obj/parser.o obj/sshell.o obj/history.o obj/hash_table.o obj/variables.o bin/record.o //<----
HEADER_FILES = include/shell.h include/parser.h include/history.h include/hash_table.h include/variables.h include/record.h
EXECUTABLE = sshell
LIBS = lib/libshell.so lib/libparser.so lib/libhistory.so lib/libhash_table.so lib/libvariables.so lib/librecord.so
LIBCFLAGS = $(CFLAGS) -D_REENTRANT -fPIC
CFLAGS = -Wall
CC = gcc
# End of configuration options
#What needs to be built to make all files and dependencies
all: $(EXECUTABLE)
#Create the main executable
$(EXECUTABLE): $(OBJS) $(LIBS)
$(CC) -o $(EXECUTABLE) obj/sshell.o -Llib -lparser -lshell -lhistory -lhash_table -lvariables -lrecord
#Create the library files
lib/libparser.so: obj/parser.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/libshell.so: obj/shutil.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/libhistory.so: obj/history.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/libhash_table.so: obj/hash_table.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/libvariables.so: obj/variables.o
$(CC) $(LIBFLAGS) -shared $^ -o $#
lib/librecord.so: bin/record.o //<----
$(CC) $(LIBFLAGS) -shared $^ -o $#
#Recursively build object files
obj/%.o: src/%.c //<---- I feel like this is causing the problem.
$(CC) $(CFLAGS) -I./include/ -c $< -o $#
#Define dependencies for objects based on header files
#We are overly conservative here, parser.o should depend on parser.h only
$(OBJS) : $(HEADER_FILES)
clean:
-rm -f $(EXECUTABLE) obj/*.o lib/*.so lib/*.a bin/*.o
-rm -f .sshell_history.txt
run: $(EXECUTABLE)
(export LD_LIBRARY_PATH=lib; ./$(EXECUTABLE))
# End of Makefile
With what I have done (most likely completely off) it doesn't compile record.c and says bin/record.o does not exist. I am not really experienced with Makefiles so I am wondering if I can have some help. Thanks!
Try using the rule .c.o instead of obj/%.o: src/%.c
Edit:
If that doesn't work, maybe adding the following rule will do the job:
bin/%.o: src/%.c
$(CC) $(CFLAGS) -I./include/ -c $< -o $#