I am working on an ARMv7 project, which has 2 cores.
According to ARM GICv2 spec. there are 16 PPIs for each core.
So my understanding is the PPI is local to each ARM core, and it should be signaled to and handled by the core.
According to ARM GICv2 spec, the PPI should have the same irq_num for all cores.
I could NOT figure out how is a PPI handled by each core.
Let me use localtimer as an example, each core has an local timer which can interrupt the connected core, in this case, how to install/register the software interrupt handler for that timer interrupt? Or there is a global interrupt handler for the interrupt targets to each core?
I found the answer to it.
As GICv2 spec. says, each PPI is private to each Core, and it is not impacted by ITARGETSRn register. Some GIC registers are banked, so each core has its own register to access.
As for the local timer example, each core should configure the same GIC registers to setup the timer interrupt, and the timer interrupt handler can be ran on each core when the PPI is triggered.
This is the local timer interrupt, which can be used as scheduling tick.
Related
In ARM architecture I have read that there are 3 kinds of interrupt :
PPI - Per processor interrupts
SPI - Shared processor interrupts
SGI - Software generated interrupts
I want to know what are these, and how they are different from each other ?
Software Generated Interrupt (SGI)
This interrupt is generated explicitly by software by writing to a dedicated distributor register, the Software Generated Interrupt Register. It is most commonly used for inter-core communication. SGIs can be targeted at all, or at a selected group of cores in the system. Interrupt numbers 0-15 are reserved for this. The software manages the exact interrupt number used for communication.
Private Peripheral Interrupt (PPI)
This interrupt is generated by a peripheral that is private to an individual core. Interrupt numbers 16-31 are reserved for this. PPIs identify interrupt sources private to the core, and are independent of the same source on another core, for example, per-core timer.
Shared Peripheral Interrupt (SPI)
This interrupt is generated by a peripheral that the Interrupt Controller can route to more than one core. Interrupt numbers 32-1020 are used for this. SPIs are used to signal interrupts from various peripherals accessible across the whole system.
You can read here
I have a specific requirement where I nee to disable my device interrupt for specific period without affecting other interrupts(code running on ARM processor). ARM document pointed that all GIC registers (related to enable, disable and clear interrupts) of ARM are Banked registers, that is there is one per CPU Interface. Banked registers accessible from the designated CPU and controls that CPU's PPI and SGI interrupts only.
What does that mean? If I disable a specific interrupt by writing to GIC register, does that get disabled only on that core or all on cores?
There are two register sets with the GIC; a banked per CPU set and the distribution (also distributor) which is system global for the GIC. For the link above, the IrqEnSet0 is a per-CPU register which is banked (again) and handles the PPI and SGI interrupts to a CPU. The IrqEnSet1 is a list of global interrupts and these maybe disable. The distribution (also distributor) can also target certain interrupts to a CPU.
ARM has many different names for these registers and different versions of the GIC. The concepts are the same for all of them. There is a set of registers that are not banked per-CPU and these control things globally including disabling the interrupts system wide. Hopefully the reader is competent enough to find and read the specific controller documentation for their SOC.
What does that mean? If I disable a specific interrupt by writing to GIC register, does that get disabled only on that core or all on cores?
PPI - peripheral private interrupt. For example, a per-CPU timer in SMP systems.
SGI - software generated interrupt. Also known as IPI on other systems. This allows signaling from one CPU to another CPU. (IPI is inter-processor interrupt).
These interrupts only make sense for each and every CPU. However, hardware like Ethernet, SPI, Video, CAN bus, i2c, ADC, etc. are usually system global.
For the distributor registers, usually the global interrupts have a read/write enable/disable. The registers for the per-CPU are probably read-only in the distributor and indicate that the interrupt is present. The other set of registers (per-CPU) are the normal mechanism to enable/disable the interrupt per-CPU. Software should have an inter-lock (semaphore) when accessing the distributor as it is global to the system. Alternatively, only an elected or boot CPU would use the distributor. The per-CPU registers are banked so a core may perform a read-modify-write without worrying about race conditions.
Reference: ARM Generic Interrupt Controller - Architecture Specification, may require registration.
I am trying to add multiprocessor support for an embedded operating system (DNA-OS) on the Zynq platform in the ZedBoard.
The OS is actually flawlessly functional with CPU_0 alone. The OS architecture requires the implementation of a cpu_send_ipi function in order to activate multiprocessing support: Basically, this function would interrupt a processor and give him a new thread to process.
I looked for an IPI register in the ug585 (Technical Reference Manual for Zynq) but couldn't find any.
I tried digging further in the Cortex-A9 spec for an IPI register, and found out that software generated interrupts could be used as IPI.
After adding software interrupt support to my OS, the problem is that CPU_0 can interrupt itself, but cannot interrupt CPU_1 !
PS: for my OS to handle SGIs, I used the register spec from the ug585 in page 1486:
So is there any other special configuration to permit CPUs to interrupt each others? or any other way to implement IPI ?
Regards,
Your reference documentation is a form of the GIC (global interrupt controller). The Cortex-A9 MP cores include an integrated GIC controller. Each CPU includes an Interrupt interface. As well, there is a system wide distributor. In order to receive the IPI (also known as SGI or software generate interrupt), you need to enable the CPU interface to receive the SGI interrupts on the 2nd CPU. This entails several steps,
Configuring the GIC interrupt interface registers on CPU2.
Setting the CP15 vector table for CPU2.
Enabling the CPSR I-bit on CPU2
Possibly setting up some banked PPI distributor registers. note1
Note1: While most distributor registers are system global, some are banked per CPU as well. For instance, see section 3.3.8. PPI Status Register in the Cortex-A9 MPcore TRM. I don't see any from a cursory investigation, but I would not rule it out.
Testing that an unused SPI (shared peripheral interrupt) works by handling the vector on CPU2 by setting the GIC distributor GICD_ISPEND register on the CPU1. This should verify that you have steps 2 and 3 covered. You may also need to set the type to ensure that they are interrupts and not FIQ; especially if you have security support. You need to use the GICD_ITARGETSR register to include CPU2.
GIC reference list
ARM Generic GIC document - registration needed, GICv1 (ignore GICv2 info).
ARM Cortex-A9 MPcore TRM - chapter 3, for specific info.
PL390 TRM - it is not spelled out anywhere, but I think this is the integrated GIC. It maybe worth looking at if you use more esoteric features.
Especially useful in the Appendix B of the Generic GIC manual. For some reason, ARM likes to keep changing the register names in each and every document they publish.
I am working on a project where i am trying to figure out how an interrupt is processed in the Global interrupt controller for a ARM architecture. I am working with pl390 interrupt controller. I see there is a line which is mentioned as legacy interrupts which bypasses the distributor logic. It is given that 2 interrupts can be programmed as a legacy interrupt. Can any one help with some explanation of what exactly is a legacy interrupt?. I trying searching online without any luck.
Legacy interrupts are the two interrupts that were in ARM before GIC arrived: nIRQ - normal interrupt request, and fIRQ - fast interrupt request.
Since legacy interrupts were made for single-core processors, and they don't support multi-core processors internally, the reason they bypass the distributor logic should be rather clear - the legacy interrupts are hardwired into one of the cores.
In short - it allows the CPU to work in backwards compatibility with older ARM specification. For example, a four-core ARM CPU will have 4 nIRQs and 4 fIRQs, separate for each of the cores. When you have an old piece of ARM-compatible hardware (which doesn't support GIC), you connect it to one of the core's nIRQ/fIRQ just as if you connected it to an old single-core CPU, and it will always execute on that one core.
More information can be found here - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CCHDBEBE.html
What is the difference between "RES: Rescheduling interrupts" and "LOC: Local timer interrupts"? What is responsible to fire the RES interrupt? Is LOC same as the general timer interrupt that is generated by the Timer h/w in the processor?
Also, please give some clarity on what part of the scheduler is invoked during the timer interrupt and the RES interrupt? How it happens in Linux kernel?
Thanks in advance.
Rescheduling interrupts are the Linux kernel's way to notify another CPU-core to schedule a thread.
On SMP systems, this is done by the scheduler to spread the load across multiple CPU-cores.
The scheduler tries to spread processor activity across as many cores as possible. The general rule of thumb is that it is preferable to have as many processes running on all the cores in lower power (lower clock frequencies) rather than have one core really busy running at full speed while other cores are sleeping.
Rescheduling interrupts are implemented using Inter-Processor Interrupts (IPI). For more details checkout this article on Rescheduling Interrupts on Linux.
Local timer interrupts are raised by the APIC for a specific CPU-core. Only that CPU-core receives the interrupts and handles them. For a brief description of its various advantages, checkout this answer.