My flash memory address is 0x2000000.
ex: If I gave mem32 0x2000000 0x4
I got read values from flash.
But I am not able to write data to flash.
I am using MX25U3235U flash memory.
I am expected to write data to flash memory through jlink command.
Related
I have been asked to help out on an embedded firmware project where they are trying to mount a file system on an SPI flash chip (Cypress S25FL512S) with a 256KB (Kilo Byte) Erase sector size.
My past experience with file systems is that the file system has a block size upto 4Kbytes which is mapped onto erase sectors of 512bytes to 4Kbytes
The embedded controller is a small NXP device running at 180MHz with 512KBytes of RAM so I cannot even cache an erase sector. I note that the chip family does have pin compatible devices with smaller erase sectors.
My general question is how do you mount a file system with a block/cluster size that is smaller than the flash erase sector size? I've not been able to find any articles addressing this.
You can't do this in any sensible way. Your specification needs to be modified.
Possible solutions are:
Pick a flash/eeprom circuit with smaller erase size.
Pick a flash/eeprom with more memory and multiple segments, so that you can back-up the data in one segment while programming another.
Add a second flash circuit which mirrors the first one, erase one at a time and overwrite with contents of the other.
Pick a MCU with more RAM.
Backup the flash inside MCU flash (very slow and likely defeats the purpose of having external flash to begin with).
STM32F4 controllers (with ARM Cortex M4 CPU) allow a so called physical remap of the lowest addresses in the memory space (0x00000000 to 0x03FFFFFF) using the SYSCFG_MEMRMP register. What I do understand is that the register selects which memory (FLASH/RAM/etc.) is aliased to the lowest addresses and therefore from which memory the reset vector and stack pointer is fetched after reset.
The documentation [1] also mentions that
In remap mode, the CPU can access the external memory via ICode bus
instead of System bus which boosts up the performance.
This means that after a remap e.g. to RAM an instruction fetched from within the alias address space (0x00000000 to 0x03FFFFFF) the ICode bus will be used.
Now my question: After such a remap operation e.g. to RAM, will a fetch to the non-aliased location of the RAM use the system bus or the ICode bus?
The background of the question is that I want to write a linker script for an image executing from RAM only (under control of a debugger). To which memory area should the .text section go? The alias space or the physical space?
[1] ST DocID018909 Rev 7
Thanks to Sean I could find the answer in the ARM® Cortex®‑M4 Processor Technical Reference Manual section 2.3.1 Bus interfaces:
ICode memory interface: Instruction fetches from Code memory space,
0x00000000 to 0x1FFFFFFC, are performed over the [sic!: this] 32-bit AHB-Lite bus.
DCode memory interface: Data and debug accesses to Code memory space,
0x00000000 to 0x1FFFFFFF, are performed over the [sic!: this] 32-bit AHB-Lite bus.
System interface: Instruction fetches and data and debug accesses to
address ranges 0x20000000 to 0xDFFFFFFF and 0xE0100000 to 0xFFFFFFFF
are performed over the [sic!: this] 32-bit AHB-Lite bus.
This also makes clear, that the flash memory of STM32F4 MCUs located at 0x08000000 is always accessed (by the CPU core) using the ICode/DCode busses, regardless if it is remapped. This is because both, the original location and the remapped location are within the code memory space (0x00000000 to 0x1FFFFFFF).
However, if the code is located in SRAM at 0x20000000 then access to the remapped location at 0x00000000 uses the ICode/DCode busses while access to the original location (outside the code memory space) uses the system bus.
The choice of bus interface on the core depends on the addresses accessed. If you access an instruction at 0x00000004, this is done on the ICode bus. An access to 0x20000004 is done using the System bus.
What the REMAP function does is change the physical memory system so that an access to 0x00000004 (ICode bus) will use the same RAM as you can also access on the system bus. Any access to 0x20000004 will be unaffected, and still be generated on the System bus by the core.
I follow some document to boot embedded Linux on ARM board (ex: Freescale Vybrid tower) via sdcard. in the document there are steps to build uImage and write u-boot into sdcard as below:
sudo dd if=u-boot.imx of=/dev/sdX bs=512 seek=2
mkimage -A arm64 -O linux -T kernel -C none -a 0x81000000 -e 0x81000000 -n
“Linux” -d Image uImage
What I would like to know is from which datasheet/UM/RM or any document they get the number: bs=512 seek=2, -a 0x81000000 (Load address), -e 0x81000000 (Entry point)
Please also explain what Load address/entry point address mean?
What I would like to know is from which datasheet/UM/RM or any document they get the number: bs=512 seek=2, -a 0x81000000 (Load address), -e 0x81000000 (Entry point)
The bs=512 seek=2 specification should be from the NXP/Freescale reference manual for the SoC (e.g. the "Expansion Device: SD, eSD and SDXC" section of the System Boot chapter).
When configured to boot from an SDcard, the ROM boot program (of the SoC) will look for a program image (e.g. U-Boot) at byte offset 0x400 (or 2 * 512 = 1024), which is the third 512-byte sector.
The first sector is presumed to be the MBR, and the second sector is reserved for an optional Secondary Image Table (using terminology from NXP document).
Allwinner SoCs use a similar booting scheme for SDcard (i.e. the U-Boot image is at a fixed location in raw sectors not part of a partition), but the image starts at the 17th sector.
Instead of loading raw sectors, some SoCs (e.g. Atmel) boot from SDcard by loading a file from a FAT partition.
Please also explain what Load address/entry point address mean?
These values are specified to the mkimage utility so that they can be installed in the uImage header. U-Boot will then use these values when the uImage is loaded and unpacked.
The load address specifies to U-Boot the required memory address to locate the image. The image is copied to that memory address.
The entry point specifies to U-Boot the memory address to jump/branch to in order to execute the image. This value is typically the same address as the load address.
For an ARM Linux kernel the recommended load and entry-point addresses are 0x8000 from the start of physical memory, according to (Vincent Sanders') Booting ARM Linux.
See Building kernel uImage using LOADADDR for more details.
Please also explain what Load address/entry point address mean?
Load address : Refers to from where the kernel is loaded. This is the kernel "load address". U-Boot shall copy the image to that region of memory. The address is dependent on the board design/architecture. In general design, this shall refer to RAM address. You need to check your board specification.
Entry point : This is where the control/execution is transferred once the image is written into RAM. (The code at this location shall will be executed first when the kernel in RAM is invoked by bootloader.)
What I would like to know is from which datasheet/UM/RM or any document they get the number: bs=512 seek=2, -a 0x81000000 (Load address), -e 0x81000000 (Entry point)
Please also explain what Load address/entry point address mean?
The bs=512 seek=2 is to skip the first sector of the SD card. This has some sort of boot information (MBR - master boot record or partition table are similar concepts) and you will brick the card if you overwrite this information (or at least need other tools to fix it). It is defined in an MMC/SD card standard. I think the JEDEC web sight has it.
The load address is where to move the SD card image to memory (Ie SDRAM). The entry point is where to hand control once the image is loaded. Often they are the same if the boot code is written in assembler and a linker is used. However, sometimes a hard coded vector table is at the start of the image and the entry point is somewhere in the middle. In any case, both are physical addresses. It could be 'IRAM' (internal static ram) for the case of a smaller kernel but must be SDRAM for Linux (which requires your SDRAM to be working). You may have issue with this if it is a custom board and not an off the shelf Vybrid Tower. Also, there are different Tower board revisions and they work differently. Check the errata on them. Finally, different U-boot versions support different boot modes. Ie, where is u-boot stored and executed from? The address are in the Vybrid TRM in the physical memory map for the Cortex-A5 CPU.
I am working on an embedded application.
Trying to configure the DMA controller I came across to the statement:
You must provide an area
of system memory to contain the channel control data structure
What do they mean saying system memory? Data SRAM? Code SRAM? Somewhere else?
You can find that statement at the beginning of section 8.4.3 here:
http://www.silabs.com/support%20documents/technicaldocs/efm32wg-rm.pdf
My understanding of it as I read it, is System Memory is allocated from the on chip RAM Memory ( Fig 3.1) not external memory mapped or flash program memory.
You see in the Table 3.2 it show the chips have Flash and internal RAM. I'd say the System Memory is the RAM, not the Flash memory.
Section 3.2 says the features of the chip is that is has 32KB of RAM on chip.
Check figure 5.2 for System Address Space. You'll need to allocate your
DMA_CTRLBASE and DMA_ALTCTRLBASE register within that region, 0x20000000 - 0x20007fff appropriately to fit the control structure. Hope that helps.
DMA measn Direct Memory Access. The idea is that a module like the ADC is not raising an iterrupt to ask the CPU to read its new data. Instead the module is directly writting on the memory of the uController. This saves performes time for the CPU. For configuration you must must create a heap structure and passing the pointer to the module. This allows the module directly change the memory content. So its your heap which is part of your SRAM.
I have ported FATFS for Free RTOS on STM32F103 SPI Flash of 32 Mbit. In a demo Application I have successfully created a file, written a file, and read back from the file. My requirement is like I have to store multiple files (images) in SPI flash and read it back when required.
I have the following conditions/queries.
I have set the Sector Size to 512 bytes, and block erase size for SPI flash is 4K. As in the SPI Flash, block needs to be erased before written. Do I need to keep track on whether a particular block is erased or not or its the file System who is managing this?
How can I verify that the sector, which I am writing in erased or not? What I am currently doing is, Erase the Complete Block for the sector, which I am going to write?
How can I make sure, The Block for SPI flash I am going to erase will not affect any Sector containing useful data?
Thanking in an Anticipation,
Regards,
AK
The simplest solution is to define the "cluster" size to 4K, the same as the page size of your flash. That mean each file, even if only 1 byte, takes 4K, which is 8 consecutive sectors of 512 bytes each.
As soon as you need to reserve one more cluster, when the file grow above 4096 bytes, you pick a free cluster, chain it to the FAT, and write the next byte.
For performance reason and to increase the durability of the flash, you should avoid to erase of flash sector when not needed. It is many order of magnitude faster to read then erasing. So, as you select a free cluster, you can start a loop to read each of the 8 sectors. As soon as you find even a single byte not equal to 0xFF, then you abort the loop and call the flash erase for that sector.
A further optimization is possible if the flash controller is able to perform the blank test directly. Such test could be done in a few microsecond while reading 8 sectors and looping to check each of the 4096 bytes is probably slower.