ESP IDF: Task never leaves vTaskDelay() - c

I am building a system that creates a WLAN AP over which the end user can Connect/disconnect the ESP to another AP ( For example a router) by posting a JSON String to a URL. In APSTA mode. When this is done a bool "_STA_START" is set to true. And the login parameters are saved in _STA_WIFI_SSID and _STA_WIFI_PASS.
I encounter a problem when writing the Task that manages the esp as Station. When the vTaskDelay() is called the code in the vTask_Manage_STA_Connection() just stops running. If I delete the statement. The code runs very fast until it casues a stack overflow and resets the esp.
start_Manage_STA_Connection() is called in main.c after I initialise the esp as Access Point.
Right now I see on the monitor that the loop in the vTask_Manage_STA_Connection runs a single time.
Below you can find my Tasks.c and Task.h
Task.h
#ifndef INCLUDE
#define INCLUDE
#include "config.h"
#endif
#ifndef INCLUDE_WLAN_STA
#define INCLUDE_WLAN_STA
#include "WLAN_STA.h"
#endif
// Dimensions the buffer that the task being created will use as its stack.
// NOTE: This is the number of words the stack will hold, not the number of
// bytes. For example, if each stack item is 32-bits, and this is set to 100,
// then 400 bytes (100 * 32-bits) will be allocated.
#define STACK_SIZE 2048
/// #brief Starts a Task to Manage the STA Connection
/// #param pvParameters
void vTask_Manage_STA_Connection( void * pvParameters );
/// #brief Calls vTask_Manage_STA_Connection in main.c
/// #param
void start_Manage_STA_Connection( void );
Tasks.c
#include "Tasks.h"
static const char *TAG_Manage_STA = "Manage STA Connection";
// Task to be created.
void vTask_Manage_STA_Connection(void *pvParameters)
{
for (;;)
{
// Task code goes here.
if (_STA_START == true)
{
ESP_LOGI(TAG_Manage_STA, "Connecting to Station...");
wifi_init_sta(
_STA_WIFI_SSID,
_STA_WIFI_PASS);
_STA_START = false;
}
ESP_LOGI(TAG_Manage_STA, "Managing STA Connection...");
vTaskDelay(100/portTICK_PERIOD_MS);
}
}
// Function that creates a task.
void start_Manage_STA_Connection(void)
{
static uint8_t ucParameterToPass;
TaskHandle_t xHandle = NULL;
// Create the task pinned to core 0, storing the handle. Note that the passed parameter ucParameterToPass
// must exist for the lifetime of the task, so in this case is declared static. If it was just an
// an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
// the new task attempts to access it.
xTaskCreatePinnedToCore(vTask_Manage_STA_Connection,
"Manage_STA_Connection",
STACK_SIZE,
&ucParameterToPass,
(configMAX_PRIORITIES-1),
&xHandle, 0);
configASSERT(xHandle);
// Use the handle to delete the task.
if (xHandle != NULL)
{
vTaskDelete(xHandle);
}
}
The Monitor Output:
I (0) cpu_start: App cpu up.
I (388) cpu_start: Pro cpu start user code
I (388) cpu_start: cpu freq: 160000000
I (388) cpu_start: Application information:
I (392) cpu_start: Project name: wifi_softAP
I (398) cpu_start: App version: 1
I (402) cpu_start: Compile time: Dec 5 2022 11:50:36
I (408) cpu_start: ELF file SHA256: 3597702b82953470...
I (414) cpu_start: ESP-IDF: v4.4.2
I (419) heap_init: Initializing. RAM available for dynamic allocation:
I (426) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (432) heap_init: At 3FFB7508 len 00028AF8 (162 KiB): DRAM
I (438) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (445) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (451) heap_init: At 400944E0 len 0000BB20 (46 KiB): IRAM
I (459) spi_flash: detected chip: gd
I (462) spi_flash: flash io: dio
I (467) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (559) MAIN: ESP_WIFI_MODE_AP/STA
I (569) WLAN AP: Wifi Loop Started
I (579) wifi:wifi driver task: 3ffc0378, prio:23, stack:6656, core=0
I (579) system_api: Base MAC address is not set
I (579) system_api: read default base MAC address from EFUSE
I (609) wifi:wifi firmware version: eeaa27d
I (609) wifi:wifi certification version: v7.0
I (609) wifi:config NVS flash: enabled
I (609) wifi:config nano formating: disabled
I (609) wifi:Init data frame dynamic rx buffer num: 32
I (619) wifi:Init management frame dynamic rx buffer num: 32
I (619) wifi:Init management short buffer num: 32
I (629) wifi:Init dynamic tx buffer num: 32
I (629) wifi:Init static rx buffer size: 1600
I (629) wifi:Init static rx buffer num: 10
I (639) wifi:Init dynamic rx buffer num: 32
I (639) wifi_init: rx ba win: 6
I (649) wifi_init: tcpip mbox: 32
I (649) wifi_init: udp mbox: 6
I (649) wifi_init: tcp mbox: 6
I (659) wifi_init: tcp tx win: 5744
I (659) wifi_init: tcp rx win: 5744
I (669) wifi_init: tcp mss: 1440
I (669) wifi_init: WiFi IRAM OP enabled
I (669) wifi_init: WiFi RX IRAM OP enabled
I (689) phy_init: phy_version 4670,719f9f6,Feb 18 2021,17:07:07
I (789) wifi:mode : sta (30:ae:a4:80:4e:88) + softAP (30:ae:a4:80:4e:89)
I (789) wifi:enable tsf
I (789) wifi:Total power save buffer number: 16
I (789) wifi:Init max length of beacon: 752/752
I (789) wifi:Init max length of beacon: 752/752
I (799) WLAN AP: Error: Unknown AP Exception
I (799) WLAN AP: wifi_init_softap finished. SSID:myssid password:mypassword channel:4
I (799) WLAN AP: Access point started!
I (819) Manage STA Connection: Managing STA Connection...
I (91529) wifi:new:<1,1>, old:<1,1>, ap:<1,1>, sta:<0,0>, prof:1
I (91529) wifi:station: 1c:bf:ce:ca:79:de join, AID=1, bgn, 40U
I (91549) WLAN AP: station 1c:bf:ce:ca:79:de join, AID=1
I (91559) esp_netif_lwip: DHCP server assigned IP to a station, IP is: 192.168.5.2
I (91559) AP Webserver: Starting webserver
I (91559) AP Webserver: Starting server on port: '80'
I (91569) AP Webserver: Registering URI handlers
W (95189) wifi:<ba-add>idx:2 (ifx:1, 1c:bf:ce:ca:79:de), tid:0, ssn:190, winSize:64

Related

How to execute debug print from within timer callback in ESP32?

I started with ESP32 last week and currently I am trying to put together the example codes for the BLE iBeacon and a 1-sec-alarm timer. I receive the error abort() was called at PC 0x403774b7 on core 0 0x403774b7: lock_acquire_generic at /home/boko/esp/esp-idf/components/newlib/locks.c:130 when running the program. I have a single ESP_LOGI() statement within the timer callback timer_alarm_cb, which seems to cause the issue, but I don't know why and how (if I remove the statment, the program works fine). What I want to achieve with the code is to get a debug print every 1 second as a visual feedback in order to know how many and which iBeacons have been detected within a 1 sec interval.
So, my 2 questions are:
Why the ESP_LOGI() statement within the timer callback causes the program to abort ?
What is the otherwise correct way to get debug print every 1 sec using a timer in ESP32?
My code is:
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
/****************************************************************************
*
* This file is for iBeacon demo. It supports both iBeacon sender and receiver
* which is distinguished by macros IBEACON_SENDER and IBEACON_RECEIVER,
*
* iBeacon is a trademark of Apple Inc. Before building devices which use iBeacon technology,
* visit https://developer.apple.com/ibeacon/ to obtain a license.
*
****************************************************************************/
#include <stdint.h>
#include <string.h>
#include <stdbool.h>
#include <stdio.h>
#include "nvs_flash.h"
#include "esp_bt.h"
#include "esp_gap_ble_api.h"
#include "esp_gattc_api.h"
#include "esp_gatt_defs.h"
#include "esp_bt_main.h"
#include "esp_bt_defs.h"
#include "esp_ibeacon_api.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h" // If you include FreeRTOS.h before task.h then portmacro.h will be included for you (do not include portmacro.h manually, just include FreeRTOS.h). However, if you fail to include FreeRTOS.h before tasks.h, then your code will not build
// #include "freertos/task.h" // BaseType_t
#include "driver/gptimer.h"
static const char* PROGRAM_NAME = "iBeacon2Omnicomm" ; // "iBeacons-ESP32-Tracker-Server" ; // "IBEACON_DEMO";
extern esp_ble_ibeacon_vendor_t vendor_config;
///Declare static functions
static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param);
#if (IBEACON_MODE == IBEACON_RECEIVER)
static esp_ble_scan_params_t ble_scan_params = {
.scan_type = BLE_SCAN_TYPE_ACTIVE,
.own_addr_type = BLE_ADDR_TYPE_PUBLIC,
.scan_filter_policy = BLE_SCAN_FILTER_ALLOW_ALL,
.scan_interval = 0x50, // 50 ms scan interval, i.e. start scanning for BLE devices every 50 ms elapsed
.scan_window = 0x30, // 30 ms scan duration, i.e. whenever a scan interval starts, keep scanning for 30 ms
.scan_duplicate = BLE_SCAN_DUPLICATE_DISABLE
};
#elif (IBEACON_MODE == IBEACON_SENDER)
static esp_ble_adv_params_t ble_adv_params = {
.adv_int_min = 0x20,
.adv_int_max = 0x40,
.adv_type = ADV_TYPE_NONCONN_IND,
.own_addr_type = BLE_ADDR_TYPE_PUBLIC,
.channel_map = ADV_CHNL_ALL,
.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY,
};
#endif
static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param)
{
esp_err_t err;
switch (event) {
case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT:{
#if (IBEACON_MODE == IBEACON_SENDER)
esp_ble_gap_start_advertising(&ble_adv_params);
#endif
break;
}
case ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT: {
#if (IBEACON_MODE == IBEACON_RECEIVER)
//the unit of the duration is second, 0 means scan permanently
uint32_t duration = 0;
ESP_LOGI(PROGRAM_NAME, "starting a scan == calling esp_ble_gap_start_scanning()");
esp_ble_gap_start_scanning(duration);
#endif
break;
}
case ESP_GAP_BLE_SCAN_START_COMPLETE_EVT:
//scan start complete event to indicate scan start successfully or failed
if ((err = param->scan_start_cmpl.status) != ESP_BT_STATUS_SUCCESS) {
ESP_LOGE(PROGRAM_NAME, "Scan start failed: %s", esp_err_to_name(err));
} else {
ESP_LOGI(PROGRAM_NAME, "Scan start successful");
}
break;
case ESP_GAP_BLE_ADV_START_COMPLETE_EVT:
//adv start complete event to indicate adv start successfully or failed
if ((err = param->adv_start_cmpl.status) != ESP_BT_STATUS_SUCCESS) {
ESP_LOGE(PROGRAM_NAME, "Adv start failed: %s", esp_err_to_name(err));
}
break;
case ESP_GAP_BLE_SCAN_RESULT_EVT: {
esp_ble_gap_cb_param_t *scan_result = (esp_ble_gap_cb_param_t *)param; // make a local copy of the passed address of parameters
switch (scan_result->scan_rst.search_evt) {
case ESP_GAP_SEARCH_INQ_RES_EVT:
/* Search for BLE iBeacon Packet */
if (esp_ble_is_ibeacon_packet(scan_result->scan_rst.ble_adv, scan_result->scan_rst.adv_data_len)){
esp_ble_ibeacon_t *ibeacon_data = (esp_ble_ibeacon_t*)(scan_result->scan_rst.ble_adv);
// ESP_LOGI("iBeacon Found:"); // error: macro "ESP_LOGI" requires 3 arguments, but only 1 given
ESP_LOGI(PROGRAM_NAME, "iBeacon Found ==========");
esp_log_buffer_hex("MAC address:", scan_result->scan_rst.bda, ESP_BD_ADDR_LEN );
esp_log_buffer_hex("UUID:", ibeacon_data->ibeacon_vendor.proximity_uuid, ESP_UUID_LEN_128);
uint16_t major = ENDIAN_CHANGE_U16(ibeacon_data->ibeacon_vendor.major);
uint16_t minor = ENDIAN_CHANGE_U16(ibeacon_data->ibeacon_vendor.minor);
ESP_LOGI(PROGRAM_NAME, "Major: 0x%04x (%d)", major, major);
ESP_LOGI(PROGRAM_NAME, "Minor: 0x%04x (%d)", minor, minor);
//ESP_LOGI(PROGRAM_NAME, "Measured power (RSSI at a 1m distance):%d dbm", ibeacon_data->ibeacon_vendor.measured_power);
ESP_LOGI(PROGRAM_NAME, "RSSI:%d dbm", scan_result->scan_rst.rssi);
}
break;
default:
break;
}
break;
}
case ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT:
if ((err = param->scan_stop_cmpl.status) != ESP_BT_STATUS_SUCCESS){
ESP_LOGE(PROGRAM_NAME, "Scan stop failed: %s", esp_err_to_name(err));
}
else {
ESP_LOGI(PROGRAM_NAME, "Stop scan successfully");
}
break;
case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT:
if ((err = param->adv_stop_cmpl.status) != ESP_BT_STATUS_SUCCESS){
ESP_LOGE(PROGRAM_NAME, "Adv stop failed: %s", esp_err_to_name(err));
}
else {
ESP_LOGI(PROGRAM_NAME, "Stop adv successfully");
}
break;
default:
break;
}
}
void ble_ibeacon_appRegister(void)
{
esp_err_t status;
ESP_LOGI(PROGRAM_NAME, "registering callback == calling esp_ble_gap_register_callback()");
//register the scan callback function to the gap module:
if ((status = esp_ble_gap_register_callback(esp_gap_cb)) != ESP_OK) {
ESP_LOGE(PROGRAM_NAME, "gap register error: %s", esp_err_to_name(status));
return;
} else {
ESP_LOGI(PROGRAM_NAME, "successful");
}
}
void ble_ibeacon_init(void)
{
esp_bluedroid_init();
esp_bluedroid_enable();
ble_ibeacon_appRegister();
}
//## BaseType_t timerOverflow = pdFALSE;
// IRAM_ATTR: Forces code into IRAM instead of flash
static bool IRAM_ATTR timer_alarm_cb ( gptimer_handle_t timer, const gptimer_alarm_event_data_t * edata, void * user_data ) { // == ISR on timer overflow event
/*
BaseType_t high_task_awoken = pdFALSE;
QueueHandle_t queue = (QueueHandle_t) user_data;
// Retrieve count value and send to queue
example_queue_element_t ele = {
.event_count = edata->count_value
};
xQueueSendFromISR(queue, &ele, &high_task_awoken);
// return whether we need to yield at the end of ISR
return (high_task_awoken == pdTRUE);
*/
//## timerOverflow = pdTRUE ; // #define pdTRUE ( ( BaseType_t ) 1 ) --> typedef portBASE_TYPE BaseType_t; --> #define portBASE_TYPE int
ESP_LOGI(PROGRAM_NAME, "1 s elapsed");
// #return Whether a high priority task has been waken up by this function:
return pdFALSE ;
}
// if prototype declared as "static bool IRAM_ATTR ..." --> error: no return statement in function returning non-void [-Werror=return-type]
void app_main(void) {
ESP_ERROR_CHECK(nvs_flash_init());
ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT));
esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
esp_bt_controller_init(&bt_cfg);
esp_bt_controller_enable(ESP_BT_MODE_BLE);
ble_ibeacon_init();
/* set scan parameters */
#if (IBEACON_MODE == IBEACON_RECEIVER)
ESP_LOGI(PROGRAM_NAME, "setting RECEIVER scan parameters == calling esp_ble_gap_set_scan_params()");
esp_ble_gap_set_scan_params(&ble_scan_params);
#elif (IBEACON_MODE == IBEACON_SENDER)
esp_ble_ibeacon_t ibeacon_adv_data;
esp_err_t status = esp_ble_config_ibeacon_data (&vendor_config, &ibeacon_adv_data);
if (status == ESP_OK){
esp_ble_gap_config_adv_data_raw((uint8_t*)&ibeacon_adv_data, sizeof(ibeacon_adv_data));
}
else {
ESP_LOGE(PROGRAM_NAME, "Config iBeacon data failed: %s\n", esp_err_to_name(status));
}
#endif
// Creating a GPTimer Handle with Resolution (frequency) of 1 MHz:
ESP_LOGI(PROGRAM_NAME, "Creating new timer (handle)");
gptimer_handle_t gptimer = NULL;
gptimer_config_t timer_config = {
.clk_src = GPTIMER_CLK_SRC_DEFAULT,
.direction = GPTIMER_COUNT_UP,
.resolution_hz = 1 * 1000 * 1000, // 1MHz, 1 tick = 1us
};
ESP_ERROR_CHECK(gptimer_new_timer(&timer_config, &gptimer));
// Prepare Triggering of Periodic Events (set up the alarm action before starting the timer !) every 1 sec:
ESP_LOGI(PROGRAM_NAME, "Setting alarm action");
gptimer_alarm_config_t alarm_config = {
.reload_count = 0, // counter will reload with 0 on alarm event
.alarm_count = 1000000, // period = 1s #resolution 1MHz
.flags.auto_reload_on_alarm = true, // enable auto-reload
};
ESP_ERROR_CHECK(gptimer_set_alarm_action(gptimer, &alarm_config));
ESP_LOGI(PROGRAM_NAME, "Registering callback function to execute on alarm event");
gptimer_event_callbacks_t cbs = {
.on_alarm = timer_alarm_cb, // register user callback
};
ESP_ERROR_CHECK(gptimer_register_event_callbacks(gptimer, &cbs, NULL));
ESP_ERROR_CHECK(gptimer_enable(gptimer));
ESP_LOGI(PROGRAM_NAME, "Starting timer");
ESP_ERROR_CHECK(gptimer_start(gptimer));
/*
while ( 1 ) {
if ( timerOverflow ) {
timerOverflow = pdFALSE ;
ESP_LOGI(PROGRAM_NAME, "1 s elapsed");
}
}
*/
}
An example terminal output is:
/home/boko/.espressif/python_env/idf5.1_py3.10_envboko#boko-HP-EliteBook-850-G8-Notebook-PC:~/Desktop/ESP32/ble_ibeacon$ export IDF_PATH=/home/boko/esp/esp-idf
boko#boko-HP-EliteBook-850-G8-Notebook-PC:~/Desktop/ESP32/ble_ibeacon$ /home/boko/.espressif/python_env/idf5.1_py3.10_env/bin/python /home/boko/esp/esp-idf/tools/idf_monitor.py -p /dev/ttyUSB0 -b 115200 --toolchain-prefix xtensa-esp32s3-elf- --target esp32s3 /home/boko/Desktop/ESP32/ble_ibeacon/build/ble_ibeacon_demo.elf
--- idf_monitor on /dev/ttyUSB0 115200 ---
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
) UUID:: fd a5�ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3810,len:0x16ac
load:0x403c9700,len:0xbc8
load:0x403cc700,len:0x2d64
entry 0x403c98fc
I (25) boot: ESP-IDF v5.1-dev-1626-g4b6d9c8ad3 2nd stage bootloader
I (25) boot: compile time Nov 11 2022 16:57:52
I (25) boot: chip revision: V001
I (29) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (36) boot.esp32s3: Boot SPI Speed : 80MHz
I (41) boot.esp32s3: SPI Mode : DIO
I (46) boot.esp32s3: SPI Flash Size : 2MB
I (51) boot: Enabling RNG early entropy source...
I (56) boot: Partition Table:
I (60) boot: ## Label Usage Type ST Offset Length
I (67) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (74) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (82) boot: 2 factory factory app 00 00 00010000 00100000
I (89) boot: End of partition table
I (93) boot_comm: chip revision: 1, min. application chip revision: 0
I (101) esp_image: segment 0: paddr=00010020 vaddr=3c080020 size=1e524h (124196) map
I (131) esp_image: segment 1: paddr=0002e54c vaddr=3fc96a00 size=01acch ( 6860) load
I (133) esp_image: segment 2: paddr=00030020 vaddr=42000020 size=7514ch (479564) map
I (223) esp_image: segment 3: paddr=000a5174 vaddr=3fc984cc size=02484h ( 9348) load
I (225) esp_image: segment 4: paddr=000a7600 vaddr=40374000 size=12998h ( 76184) load
I (253) boot: Loaded app from partition at offset 0x10000
I (253) boot: Disabling RNG early entropy source...
I (265) cpu_start: Pro cpu up.
I (265) cpu_start: Starting app cpu, entry point is 0x403753cc
0x403753cc: call_start_cpu1 at /home/boko/esp/esp-idf/components/esp_system/port/cpu_start.c:146
I (0) cpu_start: App cpu up.
I (279) cpu_start: Pro cpu start user code
I (279) cpu_start: cpu freq: 160000000 Hz
I (280) cpu_start: Application information:
I (282) cpu_start: Project name: ble_ibeacon_demo
I (288) cpu_start: App version: 1
I (293) cpu_start: Compile time: Nov 11 2022 16:57:45
I (299) cpu_start: ELF file SHA256: 2432859c4fe13f02...
I (305) cpu_start: ESP-IDF: v5.1-dev-1626-g4b6d9c8ad3
I (311) heap_init: Initializing. RAM available for dynamic allocation:
I (318) heap_init: At 3FC9E8F8 len 0004AE18 (299 KiB): D/IRAM
I (325) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
I (332) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (338) heap_init: At 600FE010 len 00001FF0 (7 KiB): RTCRAM
I (345) spi_flash: detected chip: generic
I (349) spi_flash: flash io: dio
W (353) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (366) coexist: coexist rom version e7ae62f
I (371) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (415) BT_INIT: BT controller compile version [76c24c9]
I (415) phy_init: phy_version 503,13653eb,Jun 1 2022,17:47:08
I (455) system_api: Base MAC address is not set
I (455) system_api: read default base MAC address from EFUSE
I (455) BT_INIT: Bluetooth MAC: 7c:df:a1:e3:55:fa
I (485) iBeacon2Omnicomm: registering callback == calling esp_ble_gap_register_callback()
I (485) iBeacon2Omnicomm: successful
I (485) iBeacon2Omnicomm: setting RECEIVER scan parameters == calling esp_ble_gap_set_scan_params()
I (495) iBeacon2Omnicomm: starting a scan == calling esp_ble_gap_start_scanning()
I (505) iBeacon2Omnicomm: Scan start successful
I (505) iBeacon2Omnicomm: Creating new timer (handle)
I (515) iBeacon2Omnicomm: Setting alarm action
I (515) iBeacon2Omnicomm: Registering callback function to execute on alarm event
I (525) iBeacon2Omnicomm: Starting timer
I (755) iBeacon2Omnicomm: iBeacon Found ==========
I (755) MAC address:: ac 23 3f a8 c3 a8
I (755) UUID:: fd a5 06 93 a4 e2 4f b1 af cf c6 eb 07 64 78 25
I (765) iBeacon2Omnicomm: Major: 0x08ae (2222)
I (765) iBeacon2Omnicomm: Minor: 0x08ae (2222)
I (775) iBeacon2Omnicomm: RSSI:-48 dbm
I (805) iBeacon2Omnicomm: iBeacon Found ==========
I (805) MAC address:: ac 23 3f a8 c3 a8
I (805) UUID:: fd a5 06 93 a4 e2 4f b1 af cf c6 eb 07 64 78 25
I (805) iBeacon2Omnicomm: Major: 0x04d2 (1234)
I (815) iBeacon2Omnicomm: Minor: 0x269e (9886)
I (815) iBeacon2Omnicomm: RSSI:-43 dbm
abort() was called at PC 0x403774b7 on core 0
0x403774b7: lock_acquire_generic at /home/boko/esp/esp-idf/components/newlib/locks.c:130
Backtrace: 0x40375ebe:0x3fc979f0 0x4037ec61:0x3fc97a10 0x403846a6:0x3fc97a30 0x403774b7:0x3fc97aa0 0x403775cd:0x3fc97ad0 0x4037769c:0x3fc97af0 0x420653c1:0x3fc97b20 0x42068505:0x3fc97e30 0x42075151:0x3fc97e60 0x40384555:0x3fc97e90 0x40377b75:0x3fc97ee0 0x40379d85:0x3fc97f00 0x40377295:0x3fc97f30 0x4037d8a7:0x3fcf3fb0 0x42003bc2:0x3fcf3fd0 0x40380151:0x3fcf3ff0 0x4038195d:0x3fcf4010
0x40375ebe: panic_abort at /home/boko/esp/esp-idf/components/esp_system/panic.c:423
0x4037ec61: esp_system_abort at /home/boko/esp/esp-idf/components/esp_system/esp_system.c:135
0x403846a6: abort at /home/boko/esp/esp-idf/components/newlib/abort.c:38
0x403774b7: lock_acquire_generic at /home/boko/esp/esp-idf/components/newlib/locks.c:130
0x403775cd: _lock_acquire_recursive at /home/boko/esp/esp-idf/components/newlib/locks.c:158
0x4037769c: __retarget_lock_acquire_recursive at /home/boko/esp/esp-idf/components/newlib/locks.c:314 (discriminator 3)
0x420653c1: _vfprintf_r at ??:?
0x42068505: vprintf at /builds/idf/crosstool-NG/.build/xtensa-esp32s3-elf/src/newlib/newlib/libc/stdio/vprintf.c:34 (discriminator 5)
0x42075151: esp_log_writev at /home/boko/esp/esp-idf/components/log/log.c:200
0x40384555: esp_log_write at /home/boko/esp/esp-idf/components/log/log.c:210
0x40377b75: timer_alarm_cb at /home/boko/Desktop/ESP32/ble_ibeacon/main/ibeacon_demo.c:200
0x40379d85: gptimer_default_isr at /home/boko/esp/esp-idf/components/driver/gptimer.c:512
0x40377295: _xt_lowint1 at /home/boko/esp/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vectors.S:1118
0x4037d8a7: xt_utils_wait_for_intr at /home/boko/esp/esp-idf/components/xtensa/include/xt_utils.h:81
(inlined by) esp_cpu_wait_for_intr at /home/boko/esp/esp-idf/components/esp_hw_support/cpu.c:115
0x42003bc2: esp_vApplicationIdleHook at /home/boko/esp/esp-idf/components/esp_system/freertos_hooks.c:59
0x40380151: prvIdleTask at /home/boko/esp/esp-idf/components/freertos/FreeRTOS-Kernel/tasks.c:4273 (discriminator 1)
0x4038195d: vPortTaskWrapper at /home/boko/esp/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:152
ELF file SHA256: 2432859c4fe13f02
Rebooting...
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x3 (RTC_SW_SYS_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
Saved PC:0x4037585c
0x4037585c: esp_restart_noos_dig at /home/boko/esp/esp-idf/components/esp_system/esp_system.c:46 (discriminator 1)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3810,len:0x16ac
load:0x403c9700,len:0xbc8
load:0x403cc700,len:0x2d64
entry 0x403c98fc
I (29) boot: ESP-IDF v5.1-dev-1626-g4b6d9c8ad3 2nd stage bootloader
I (29) boot: compile time Nov 11 2022 16:57:52
I (30) boot: chip revision: V001
I (34) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (41) boot.esp32s3: Boot SPI Speed : 80MHz
I (46) boot.esp32s3: SPI Mode : DIO
I (50) boot.esp32s3: SPI Flash Size : 2MB
I (55) boot: Enabling RNG early entropy source...
I (60) boot: Partition Table:
I (64) boot: ## Label Usage Type ST Offset Length
I (79) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (86) boot: 2 factory factory app 00 00 00010000 00100000
I (94) boot: End of partition table
I (98) boot_comm: chip revision: 1, min. application chip revision: 0
I (105) esp_image: segment 0: paddr=00010020 vaddr=3c080020 size=1e524h (124196) map
I (136) esp_image: segment 1: paddr=0002e54c vaddr=3fc96a00 size=01acch ( 6860) load
I (138) esp_image: segment 2: paddr=00030020 vaddr=42000020 size=7514ch (479564) map
I (228) esp_image: segment 3: paddr=000a5174 vaddr=3fc984cc size=02484h ( 9348) load
I (230) esp_image: segment 4: paddr=000a7600 vaddr=40374000 size=12998h ( 76184) load
I (258) boot: Loaded app from partition at offset 0x10000
I (258) boot: Disabling RNG early entropy source...
I (269) cpu_start: Pro cpu up.
I (269) cpu_start: Starting app cpu, entry point is 0x403753cc
0x403753cc: call_start_cpu1 at /home/boko/esp/esp-idf/components/esp_system/port/cpu_start.c:146
I (0) cpu_start: App cpu up.
I (284) cpu_start: Pro cpu start user code
I (284) cpu_start: cpu freq: 160000000 Hz
I (284) cpu_start: Application information:
I (287) cpu_start: Project name: ble_ibeacon_demo
I (293) cpu_start: App version: 1
I (297) cpu_start: Compile time: Nov 11 2022 16:57:45
I (303) cpu_start: ELF file SHA256: 2432859c4fe13f02...
I (309) cpu_start: ESP-IDF: v5.1-dev-1626-g4b6d9c8ad3
I (316) heap_init: Initializing. RAM available for dynamic allocation:
I (323) heap_init: At 3FC9E8F8 len 0004AE18 (299 KiB): D/IRAM
I (329) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
I (336) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (342) heap_init: At 600FE010 len 00001FF0 (7 KiB): RTCRAM
I (349) spi_flash: detected chip: generic
I (353) spi_flash: flash io: dio
W (357) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (371) coexist: coexist rom version e7ae62f
I (375) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (420) BT_INIT: BT controller compile version [76c24c9]
I (420) phy_init: phy_version 503,13653eb,Jun 1 2022,17:47:08
I (460) system_api: Base MAC address is not set
I (460) system_api: read default base MAC address from EFUSE
I (460) BT_INIT: Bluetooth MAC: 7c:df:a1:e3:55:fa
I (490) iBeacon2Omnicomm: registering callback == calling esp_ble_gap_register_callback()
I (490) iBeacon2Omnicomm: successful
I (490) iBeacon2Omnicomm: setting RECEIVER scan parameters == calling esp_ble_gap_set_scan_params()
I (500) iBeacon2Omnicomm: starting a scan == calling esp_ble_gap_start_scanning()
I (510) iBeacon2Omnicomm: Scan start successful
I (510) iBeacon2Omnicomm: Creating new timer (handle)
I (520) iBeacon2Omnicomm: Setting alarm action
I (520) iBeacon2Omnicomm: Registering callback function to execute on alarm event
I (530) iBeacon2Omnicomm: Starting timer
I (580) iBeacon2Omnicomm: iBeacon Found ==========
I (580) MAC address:: ac 23 3f a8 c3 a8
I (580) UUID:: fd a5 06 93 a4 e2 4f b1 af cf c6 eb 07 64 78 25
I (590) iBeacon2Omnicomm: Major: 0x2711 (10001)
I (590) iBeacon2Omnicomm: Minor: 0x4cb9 (19641)
I (600) iBeacon2Omnicomm: RSSI:-37 dbm
I (1220) iBeacon2Omnicomm: iBeacon Found ==========
I (1220) MAC address:: ac 23 3f a8 c3 a8
I (1220) UUID:: fd a5 06 93 a4 e2 4f b1 af cf c6 eb 07 64 78 25
I (1230) iBeacon2Omnicomm: Major: 0x04d2 (1234)
I (1230) iBeacon2Omnicomm: Minor: 0x269e (9886)
I (1240) iBeacon2Omnicomm: RSSI:-51 dbm
abort() was called at PC 0x403774b7 on core 0
0x403774b7: lock_acquire_generic at /home/boko/esp/esp-idf/components/newlib/locks.c:130
Backtrace: 0x40375ebe:0x3fc979f0 0x4037ec61:0x3fc97a10 0x403846a6:0x3fc97a30 0x403774b7:0x3fc97aa0 0x403775cd:0x3fc97ad0 0x4037769c:0x3fc97af0 0x420653c1:0x3fc97b20 0x42068505:0x3fc97e30 0x42075151:0x3fc97e60 0x40384555:0x3fc97e90 0x40377b75:0x3fc97ee0 0x40379d85:0x3fc97f00 0x40377295:0x3fc97f30 0x4037d8a7:0x3fcf3fb0 0x42003bc2:0x3fcf3fd0 0x40380151:0x3fcf3ff0 0x4038195d:0x3fcf4010
0x40375ebe: panic_abort at /home/boko/esp/esp-idf/components/esp_system/panic.c:423
0x4037ec61: esp_system_abort at /home/boko/esp/esp-idf/components/esp_system/esp_system.c:135
0x403846a6: abort at /home/boko/esp/esp-idf/components/newlib/abort.c:38
0x403774b7: lock_acquire_generic at /home/boko/esp/esp-idf/components/newlib/locks.c:130
0x403775cd: _lock_acquire_recursive at /home/boko/esp/esp-idf/components/newlib/locks.c:158
0x4037769c: __retarget_lock_acquire_recursive at /home/boko/esp/esp-idf/components/newlib/locks.c:314 (discriminator 3)
0x420653c1: _vfprintf_r at ??:?
0x42068505: vprintf at /builds/idf/crosstool-NG/.build/xtensa-esp32s3-elf/src/newlib/newlib/libc/stdio/vprintf.c:34 (discriminator 5)
0x42075151: esp_log_writev at /home/boko/esp/esp-idf/components/log/log.c:200
0x40384555: esp_log_write at /home/boko/esp/esp-idf/components/log/log.c:210
0x40377b75: timer_alarm_cb at /home/boko/Desktop/ESP32/ble_ibeacon/main/ibeacon_demo.c:200
0x40379d85: gptimer_default_isr at /home/boko/esp/esp-idf/components/driver/gptimer.c:512
0x40377295: _xt_lowint1 at /home/boko/esp/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/xtensa_vectors.S:1118
0x4037d8a7: xt_utils_wait_for_intr at /home/boko/esp/esp-idf/components/xtensa/include/xt_utils.h:81
(inlined by) esp_cpu_wait_for_intr at /home/boko/esp/esp-idf/components/esp_hw_support/cpu.c:115
0x42003bc2: esp_vApplicationIdleHook at /home/boko/esp/esp-idf/components/esp_system/freertos_hooks.c:59
0x40380151: prvIdleTask at /home/boko/esp/esp-idf/components/freertos/FreeRTOS-Kernel/tasks.c:4273 (discriminator 1)
0x4038195d: vPortTaskWrapper at /home/boko/esp/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:152
You're trying to log from within a General Purpose Timer interrupt. Quoting from documentation for Logging library:
This function or these macros should not be used from an interrupt.
There's also a longer comment from an Espressif developer explaining why. There seems to be another macro ESP_DRAM_LOGE for printing from within an interrupt (which is usually not a good idea).
Anyway, for anything except the most stringent real-time criteria I'd recommend using the High Resolution Timer instead. It's still run on top of the hardware timer peripheral, but processing of callbacks is deferred to a dedicated timer task (yes, you have to wait for a short time until the scheduler gets around to executing that task). This means your callbacks run in a regular task and can call logging functions. Don't go overboard - you still want the deferred timer callbacks to be reasonably quick to avoid timing jittering.

DMA writing to allocated memory misses the first two adresses on the first write

I'm playing around with a ZYNQ7 (Dual-Core ARM) with a FPGA. The FPGA design has a 32-bit counter accessing the DDR via a DMA controller in chunks of 256-packets.
In the C-Code for the processor 1, I run a LWIP application to connect via ethernet to my pc.
There I allocate ram memory for the DMA transactions. The address of the pointer is passed via shared memory to the 2nd Core.
#define RCVADDR 0x1ef00002
u32_t * send=NULL;
u32_t* addr = (uint32_t*)RCVADDR;
//Allocating the memory once initially
if(send==NULL){
send=malloc(256*sizeof(uint32_t));
}
*addr = (uint32_t)send;
//starting the DMA on Core 2
*getdma=1;
Using a handshake I initialize the DMA transactions in the second core and send the Data after finished transactions to the PC using a TCP connection on the 1st Core.
#define GetDMA 0x1ef00001
#define DONEDMA 0x1ef00003
uint8_t* getdma = (uint8_t*)GetDMA;
uint32_t* addr=(uint32_t*)RCVADDR;
while(1){
if(*getdma == 1){
StartDMATransfer(*addr, 2048); // The Number 2048 is the number Of Transfered Packets. It has to be at least the amount of Packets my Counter transfers in chunks. The design has a packet end indicator on its own. So 256 or bigger works the same as 256
*getdma =0;
Xil_DCacheFlush();
}
}
Before establishing a TCP-connection I flush the DCache
void send_data(){
int ip_addr[4];
u8_t i=0;
char * token = strtok(ip,".");
ip_addr[0] = atoi(token);
while(token != NULL){
ip_addr[++i]=atoi(strtok(NULL,"."));
}
Xil_DCacheFlushRange(send, 256*sizeof(uint32_t));
//sleep(0.5);
connect(ip_addr,atoi(port));
}
The Problem: The first Transmission Cycle after programming the Device shows:
[1280, 1281, 2, 3, 4, 5, 6,.....
....., 248, 249,1530, 1531, 1532, 1533, 1534, 1535]
The first 2 Values and the last 6 values are from a previous Cycle before reprogramming the device.
However, this only occurs on the first DMA Transaction. Afterwards, while the device runs it never occurs once again.
Any Ideas?
I found a solution....
I had to flush the Cache after allocating the memory, before passing the address to the 2nd Core for processing.

C code memory alignment issue on embedded system?

After a major refactoring of an embedded system (IAR C on TI CC2530), I've ended up in the following situation:
After basic initialization of peripherals and global interrupt enable, the execution incorrectly ends up in an interrupt handler that communicates with external hardware. Since this hardware is not ready (remember, we end up in the ISR incorrectly), the program freezes triggering a watchdog reset.
If I insert 1, 2, 3, 5, 6, 7 etc NOPs in main(), everything works fine.
But If I insert 0, 4, 8 etc NOPs, I get the faulty behaviour.
CC2530 fetches 4 bytes of instructions from flash memory, on 4-byte boundaries.
This tells me that something is misaligned when it comes to code memory, but I simply doesn't know where to start. Nothing has changed when it comes the target settings AFAIK.
Anyone here who has seen this situation before, or can point me in the right direction?
#include <common.h>
#include <timer.h>
#include <radio.h>
#include <encryption.h>
#include "signals.h"
#include "lock.h"
#include "nfc.h"
#include "uart1_trace.h"
#include "trace.h"
//------------------------------------------------------------------------------
// Public functions
//------------------------------------------------------------------------------
void main(void)
{
setTp;
// Initialize microcontroller and peripherals
ClockSourceInit();
WatchdogEnable();
PortsInit();
TraceInit();
Timer4Init();
SleepInit();
RadioInit();
Uart1Init();
LoadAesKey("\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0");
clrTp;
NfcInit();
__enable_interrupt();
asm("nop");
// Initialize threads
LockInit();
while (true)
{
WDR();
LockRun();
}
}
void NfcInit(void)
{
// Enable wake up interrupt on external RF field present
// The process for enabling interrupts is described in section 2.5.1 in the CC2530 datasheet.
// Configure interrupt source: interrupt on falling edge, Port 0, pin 7:0
PICTL |= BIT(0);
// 1. Clear port 0 individual interrupt flag. Read-modify-write is not allowed.
// Writing 1 to a bit in this register has no effect, so 1 should be written to flags that are not to be cleared.
P0IFG = ~BIT(3);
// Clear port 0 interrupt flag. This register is bit-accessible.
P0IF = 0;
// 2. Set pin 3 interrupt-enable
P0IEN |= BIT(3);
// 3. Set port 0 interrupt-enable
IEN1 |= BIT(5);
// 4. Global interrupt enable is set in main()
}
// Interrupt handler: falling edge on signal Wake.
// This interrupt will only occur when device is powered off and NFC field present.
// When device is powered on, VCORE is always asserted.
#pragma vector = 0x6B
__interrupt static void NFC_WAKE_ISR(void)
{
static uint16 cnt = 0;
TracePutUint16(cnt); TracePuts("\r\n");
if (++cnt > 10)
IEN1 &= ~BIT(5);
P0IFG = ~BIT(3); // Clear port 1 individual interrupt flag. Read-modify-write is not allowed.
P0IF = 0; // Clear port 1 CPU interrupt flag. This register is bit-accessible.
return;
Screenshot of software init.
CH1 = External interrupt signal, active low (signal Wake).
CH2 = TP in main.c (setTp / clrTp).
The reset button on CC-debugger seems not to be debounced, so the TP signal turns on and off a few times before stabilizing (should not be an issue). VCC is stable long before the reset. When TP goes low for the last time, all peripherals are initialized.
An external NFC IC is used to wake up the MCU from sleep mode when a NFC field is present. The NFC IC is powered by one of the CC2530 I/O-pins. Normally the IC is powered off to preserve power. In this state, the energy from the NFC field is enough to generate the wake signal (active low). When this signal is detected by the MCU, it wakes up, applies power to the NFC IC, and NFC communication starts.
The NFC IC generates the signal either when powered, or when a NFC field is present.
After reset, all I/O-pins are configured as inputs with pullups. This pulled up input is enough to power the NFC IC, which is why the wake-signal is generated. Immediatly after reset, the I/O is configured (in function PortsInit()), and power to NFC IC is turned off. This makes the wake signal go low. The slow rise- and fall times are probably due to a capacitor, that I will now remove.
Here is where things get weird. Despite the wake signal being low, the external interrupt is configured for falling edge and pending int flag is cleared right before global in enabled, I end up in the ISR a few ms later (not seen in the screen shot). But only with the right number of NOPs, as described above.
If I add a > 15 ms delay before global int enable, all is fine. This coincides with the time measured from TP low to wake high.
One might think that the int is incorrectly configured for active low, but in that case I should get multiple ints, and I don't. Also, that does not explain the magic NOPs...
Compiler generated ISR assembly code:
// 77 // Interrupt handler: falling edge on signal Wake.
// 78 // This interrupt will only occur when device is powered off and NFC field present.
// 79 // When device is powered on, VCORE is always asserted.
// 80 #pragma vector = 0x6B
RSEG NEAR_CODE:CODE:NOROOT(0)
// 81 __interrupt static void NFC_WAKE_ISR(void)
NFC_WAKE_ISR:
// 82 {
PUSH A
MOV A,#-0xe
LCALL ?INTERRUPT_ENTER_XSP
; Saved register size: 15
; Auto size: 0
// 83 static uint16 cnt = 0;
// 84
// 85 TracePutUint16(cnt); TracePuts("\r\n");
; Setup parameters for call to function PutUint16
MOV R4,#(TPutc & 0xff)
MOV R5,#((TPutc >> 8) & 0xff)
MOV DPTR,#??cnt
MOVX A,#DPTR
MOV R2,A
INC DPTR
MOVX A,#DPTR
MOV R3,A
LCALL PutUint16
; Setup parameters for call to function TPuts
MOV R2,#(`?<Constant "\\r\\n">` & 0xff)
MOV R3,#((`?<Constant "\\r\\n">` >> 8) & 0xff)
LCALL TPuts
// 86
// 87 if (++cnt > 10)
MOV DPTR,#??cnt
MOVX A,#DPTR
ADD A,#0x1
MOV R0,A
INC DPTR
MOVX A,#DPTR
ADDC A,#0x0
MOV R1,A
MOV DPTR,#??cnt
MOV A,R0
MOVX #DPTR,A
INC DPTR
MOV A,R1
MOVX #DPTR,A
CLR C
MOV A,R0
SUBB A,#0xb
MOV A,R1
SUBB A,#0x0
JC ??NFC_WAKE_ISR_0
// 88 IEN1 &= ~BIT(5);
CLR 0xb8.5
// 89
// 90
// 91 P0IFG = ~BIT(3); // Clear port 1 individual interrupt flag. Read-modify-write is not allowed.
??NFC_WAKE_ISR_0:
MOV 0x89,#-0x9
// 92 P0IF = 0; // Clear port 1 CPU interrupt flag. This register is bit-accessible.
CLR 0xc0.5
// 93
// 94 return;
MOV R7,#0x1
LJMP ?INTERRUPT_LEAVE_XSP
REQUIRE _A_P0
REQUIRE P0IFG
REQUIRE _A_P1
REQUIRE _A_IEN1
REQUIRE _A_IRCON
////////////////////////////////////////////////////////////////////////////////
// lnk51ew_CC2530F64.xcl: linker command file for IAR Embedded Workbench IDE
// Generated: Mon May 24 00:00:01 +0200 2010
//
////////////////////////////////////////////////////////////////////////////////
//
// Segment limits
// ==============
//
// IDATA
// -----
-D_IDATA0_START=0x00
-D_IDATA0_END=0xFF
//
// PDATA
// -----
// We select 256 bytes of (I)XDATA memory that can be used as PDATA (see also "PDATA page setup" below)
-D_PDATA0_START=0x1E00
-D_PDATA0_END=0x1EFF
//
//
// IXDATA
// ------
-D_IXDATA0_START=0x0001 // Skip address 0x0000 (to avoid ambiguities with NULL pointer)
-D_IXDATA0_END=0x1EFF // CC2530F64 has 8 kB RAM (NOTE: 256 bytes are used for IDATA)
//
//
// XDATA
// -----
-D_XDATA0_START=_IXDATA0_START
-D_XDATA0_END=_IXDATA0_END
//
// NEAR CODE
// ---------
-D_CODE0_START=0x0000
-D_CODE0_END=0xFFFF // CC2530F64 has 64 kB code (flash)
//
// Special SFRs
// ============
//
// Register bank setup
// -------------------
-D?REGISTER_BANK=0x0 // Sets default register bank (0,1,2,3)
-D_REGISTER_BANK_START=0x0 // Start address for default register bank (0x0, 0x8, 0x10, 0x18)
//
// PDATA page setup
// ----------------
-D?PBANK_NUMBER=0x1E // High byte of 16-bit address to the PDATA area
//
// Virtual register setup
// ----------------------
-D_BREG_START=0x00
-D?VB=0x20
-D?ESP=0x9B //Extended stack pointer register location
////////////////////////////////////////////////////////////////////////////////
//
// IDATA memory
// ============
-Z(BIT)BREG=_BREG_START
-Z(BIT)BIT_N=0-7F
-Z(DATA)REGISTERS+8=_REGISTER_BANK_START
-Z(DATA)BDATA_Z,BDATA_N,BDATA_I=20-2F
-Z(DATA)VREG+_NR_OF_VIRTUAL_REGISTERS=08-7F
-Z(DATA)PSP,XSP=08-7F
-Z(DATA)DOVERLAY=08-7F
-Z(DATA)DATA_I,DATA_Z,DATA_N=08-7F
-U(IDATA)0-7F=(DATA)0-7F
-Z(IDATA)IDATA_I,IDATA_Z,IDATA_N=08-_IDATA0_END
-Z(IDATA)ISTACK+_IDATA_STACK_SIZE#08-_IDATA0_END
-Z(IDATA)IOVERLAY=08-FF
//
// ROM memory
// ==========
//
// Top of memory
// -------------
-Z(CODE)INTVEC=0
-Z(CODE)CSTART=_CODE0_START-_CODE0_END
//
// Initializers
// ------------
-Z(CODE)BIT_ID,BDATA_ID,DATA_ID,IDATA_ID,IXDATA_ID,PDATA_ID,XDATA_ID=_CODE0_START-_CODE0_END
//
// Program memory
// --------------
-Z(CODE)RCODE,DIFUNCT,CODE_C,CODE_N,NEAR_CODE=_CODE0_START-_CODE0_END
//
// Checksum
// --------
-Z(CODE)CHECKSUM#_CODE0_END
//
// XDATA memory
// ============
//
// Stacks located in XDATA
// -----------------------
-Z(XDATA)EXT_STACK+_EXTENDED_STACK_SIZE=_EXTENDED_STACK_START
-Z(XDATA)PSTACK+_PDATA_STACK_SIZE=_PDATA0_START-_PDATA0_END
-Z(XDATA)XSTACK+_XDATA_STACK_SIZE=_XDATA0_START-_XDATA0_END
//
// PDATA - data memory
// -------------------
-Z(XDATA)PDATA_Z,PDATA_I=_PDATA0_START-_PDATA0_END
-P(XDATA)PDATA_N=_PDATA0_START-_PDATA0_END
//
// XDATA - data memory
// -------------------
-Z(XDATA)IXDATA_Z,IXDATA_I=_IXDATA0_START-_IXDATA0_END
-P(XDATA)IXDATA_N=_IXDATA0_START-_IXDATA0_END
-Z(XDATA)XDATA_Z,XDATA_I=_XDATA0_START-_XDATA0_END
-P(XDATA)XDATA_N=_XDATA0_START-_XDATA0_END
-Z(XDATA)XDATA_HEAP+_XDATA_HEAP_SIZE=_XDATA0_START-_XDATA0_END
-Z(CONST)XDATA_ROM_C=_XDATA0_START-_XDATA0_END
//
// Core
// ====
-cx51
////////////////////////////////////////////////////////////////////////////////
//
// Texas Instruments device specific
// =================================
//
// Flash lock bits
// ---------------
//
// The CC2530 has its flash lock bits, one bit for each 2048 B flash page, located in
// the last available flash page, starting 16 bytes from the page end. The number of
// bytes with flash lock bits depends on the flash size configuration of the CC2530
// (maximum 16 bytes, i.e. 128 page lock bits, for the CC2530 with 256 kB flash).
// Note that the bit that controls the debug interface lock is always in the last byte,
// regardless of flash size.
//
-D_FLASH_LOCK_BITS_START=(_CODE0_END-0xF)
-D_FLASH_LOCK_BITS_END=_CODE0_END
//
// Define as segment in case one wants to put something there intentionally (then comment out the trick below)
-Z(CODE)FLASH_LOCK_BITS=_FLASH_LOCK_BITS_START-_FLASH_LOCK_BITS_END
//
// Trick to reserve the FLASH_LOCK_BITS segment from being used as normal CODE, avoiding
// code to be placed on top of the flash lock bits. If code is placed on address 0x0000,
// (INTVEC is by default located at 0x0000) then the flash lock bits will be reserved too.
//
-U(CODE)0x0000=(CODE)_FLASH_LOCK_BITS_START-_FLASH_LOCK_BITS_END
//
////////////////////////////////////////////////////////////////////////////////
According to TI, that part has got an 8051 core. Apart from being dinosaur crap, 8051 is an 8-bitter so alignment does not apply.
When random modifications to the code result in completely unrelated errors or run-away code, it is most often caused by one of these things:
You got a stack overflow, or
You got undefined behavior bugs, such as uninitialized variables, array out of bounds access etc.
Also ensure that all ISRs are registred in the interrupt vector table.
EDIT after question change 6/4:
You should normally not return from interrupts! I don't know how your specific setup works, but with a general embedded systems compiler, the non-standard interrupt keyword means two things:
Ensure that the calling convention upon entering the ISR is correct, by stacking whatever registers the CPU/ABI state are not stacked by hardware, but software.
Ensure that the same registers are restored upon leaving the ISR and that the correct return instruction is used.
On 8051 this means that the disassembled ISR absolutely must end with a RETI instruction and not a RET instruction! Chances are high that return results in RET which will sabotage your stack. Disassemble to see if this is indeed the case.
The user's guide for the CC2530 states:
The instruction that sets the PCON.IDLE bit must be aligned in a
certain way for correct operation. The first byte of the assembly
instruction immediately following this instruction must not be placed
on a 4-byte boundary.
This is likely why the system fails on NOP multiples of four.
Just below the warning, there is an implementation for fixing this alignment specifically targeted at the IAR compiler.
I am starting to believe that this is a hardware issue, related to the connection between CC2530 and the NFC IC.
The power and reset to the NFC IC that sends the external interrupt request is controlled by a CC2530 I/O pin with 20 mA current drive capacity. At reset, before execution of the program starts, all the I/O pins defaults to inputs with internal weak pull-up. It seems like the current through the pull-up resistor is enough to power up the NFC IC. The interrupt signal from the NFC IC is high whenever the NFC is powered or a NFC field is present, and inverted by a FET transistor before reaching CC2530. Hence the ISR is triggered by a falling edge on the input.
So what happens at startup is that the NFC IC is incorrectly powered on (and later off, when the ports are initialized), and the WAKE signal falls and rises very slowly due to the poor drive capacity of a pull-up (to make things worse, a large capacitor of 1 uF is connected in parallel with the gate of the FET, and another 1uF filters the NFC IC power pin).
WAKE is supposed to trigger an interrupt only on falling edge, but staying in the transition region for up to 10 ms as seen in the oscilloscope screenshot above seems to cause CC2530 to fire the interrupt even when WAKE is rising. The ISR starts to communicate with the NFC IC via SPI, but at this time, the NFC IC seems to be messed up due to the spurious transitions on VCC and reset. It refuses to respond, the execution halts in the ISR and the watchdog bites. And the process starts over, forever.
When I insert a delay that ensures WAKE to be stable high before enabling the interrupt, all is well.
If I remove the 1 uF cap on the FET gate, WAKE rises very quickly, and there is no need for the delay anymore. And when I add a 4k7 pulldown to the NFC power, it is no longer powered up at reset.
Problem seems to be solved. The refactoring rearranged the code and changed the startup sequence, which led to a different delay that revealed the issue. With the proper hardware update, no delay will be needed.
But what still disturbes me is that I don't understand the magic NOPs. When CC2530 had the interrupt enabled and encountered a slowly rising WAKE, it wouldn't always end up incorrectly in the ISR. And when it did, I could always make it run by adding 1..3 NOPs. Naturally, whenever I added or removed a line of code, the number of NOPs required changed, which as you can imagine, drove me crazy.
It took me some time to narrow things down, and I am very grateful to all your comments and proposed solutions, especially Clifford that forced me to bring out the oscilloscope.

Can't start SMP AP processors in MINIX: startup_IPI restarts and hangs

i'm running minix 3.1.2a ,my goal is to start APs procesoors other than the BSP ,i followed the universal startup algorithm :
BSP sends AP an INIT IPI
BSP DELAYs (10mSec)
BSP sends AP a STARTUP IPI
BSP DELAYs (200μSEC)
BSP sends AP a STARTUP IPI
BSP DELAYs (200μSEC)
here's the Function to do INIT IPI AND STARTUP IPI after reading the ACPI table:
void START_APs2()
{
u32_t trampoline_addr;
int UseCPU = 1;
u32_t reg;
/* Try to allocate the trampoline for APs to start */
if ((trampoline_addr=find_trampoline()))
{
reg = LOCAL_APIC_READ(LOCAL_APIC_SPIV);
reg |= 0x1FF; /* Disable apic */
LOCAL_APIC_WRITE(LOCAL_APIC_SPIV, reg);
/*======================== INIT IPI==============================*/
CLI();
/*LOCAL_APIC_WRITE(LOCAL_APIC_ICR_HIGH, (unsigned long)cpus[UseCPU].ApicID << 24);*/
LOCAL_APIC_WRITE(LOCAL_APIC_ICR_LOW, (unsigned long) (0x4500) | (trampoline_addr>>12)|(DEST_OTHERS << DEST_SHORT_SHIFT));
/*wait_for_ipi_completion();*/
VerifyLoop();
/*Some delay ...*/
milli_delay(100);
/*=============================STARTUP IPI==============================*/
/* LOCAL_APIC_WRITE(LOCAL_APIC_ICR_HIGH, (unsigned long)cpus[UseCPU].ApicID <<24);*/
LOCAL_APIC_WRITE(LOCAL_APIC_ICR_LOW, (unsigned long) (0x5600) | (trampoline_addr>>12)|(DEST_OTHERS << DEST_SHORT_SHIFT));
VerifyLoop();
/*Some delay ...*/
milli_delay(200);
/* send the IPI */
/*LOCAL_APIC_WRITE(LOCAL_APIC_ICR_HIGH, (unsigned long)cpus[UseCPU].ApicID <<24);*/
LOCAL_APIC_WRITE(LOCAL_APIC_ICR_LOW, (unsigned long) (0x5600) | (trampoline_addr>>12)|(DEST_OTHERS << DEST_SHORT_SHIFT));
VerifyLoop();
/*Some delay ...*/
milli_delay(200);
STI();
/* enable_cpu(this_cpu, WITHOUT_ECHO);*/
if (! AP_running())
{
Aprintf(("\n\n*** WARNING! AP# %d is not running ***\n\n",(unsigned long)cpus[UseCPU].ApicID));
}
else
{
Aprintf("\n\n***AP RUNNING SUCCESSFULLY");
}
}
}
i'd like to note that i run on a core i7 host machine with windows 7 ,64-bit
and i have 3 different virtual M/Cs :
VMWARE WORKSTATION
VBOX
QEMU MANAGER
1-on VMWARE:
mainly i run my guest minix on VMWARE ,when i run the previously mentioned code :
when i choose the number of processors i.e 4 and number of cores
1,and run that code the system will keep in restarting.
when i choose the number of processors i.e 1 and number of cores
4,and run that code the system will hang.
2-on VBOX:
when i choose the number of processors 4 and run that code the system will hang.
3-on QEMU:
first the acpi checksum is incorrect ,so i enter the CPUAPIC ID manually just to test i.e APIC ID =1
- when i choose the number of cpus 4 ,and run that code the system will hang.
actually i stuck in that problem for more than 10 days and i pull out my all hair ,i can't reconize why is not starting ,so if any one can help i'll be appreciated

Intel Galileo bare metal UART

I want to program a little "hello world" bare metal application on the Intel Galileo board. Using UEFI to print out text (to UART-1) works well, of course, but I want to access the UART "manually", without any help from UEFI.
In QEMU my code works well:
.h file
#define COM1_PORT (0x03F8)
#define UART_PORT (COM1_PORT)
enum uart_port_offs_t
{ // DLAB RW
THR = 0, // 0 W Transmitter Holding Buffer
RBR = 0, // 0 R Receiver Buffer
DLL = 0, // 1 RW Divisor Latch Low Byte
IER = 1, // 0 RW Interrupt Enable Register
DLH = 1, // 1 RW Divisor Latch High Byte
IIR = 2, // - R Interrupt Identification Register
FCR = 2, // - RW FIFO Control Register
LCR = 3, // - RW Line Control Register
MCR = 4, // - RW Modem Control Register
LSR = 5, // - R Line Status Register
MSR = 6, // - R Modem Status Register
SR = 7, // - RW Scratch Register
};
.c file
void uart_init(void)
{
outb(UART_PORT + IER, 0x00); // Disable all interrupts
outb(UART_PORT + LCR, LCR_DLAB);
outb(UART_PORT + DLL, BAUD_LL); // Set divisor (lo byte)
outb(UART_PORT + DLH, BAUD_HL); // (hi byte)
outb(UART_PORT + LCR, LCR_WORD_BITS_8 | LCR_PAR_NONE | LCR_STOP_BITS_1);
outb(UART_PORT + FCR, FCR_ENABLE | FCR_CLR_RECV | FCR_CLR_SEND | FCR_TRIGGER_16);
outb(UART_PORT + MCR, MCR_DSR | MCR_RTS | MCR_AUX2);
}
ssize_t uart_write(const char *buf, size_t len)
{
size_t written = 0;
while (written < len) {
while (!is_output_empty()) {
asm volatile ("pause");
}
outb(UART_PORT + THR, buf[written]);
++written;
}
return written;
}
main
SystemTable->ConOut->OutputString(SystemTable->ConOut, L"Exiting EFI boot services ...\r\n");
SystemTable->BootServices->ExitBootServices(ImageHandle, map_key);
uart_init();
while (1) {
const char s[] = "UART\r\n";
uart_write(s, sizeof (s) - 1);
}
The specs did not help me very much. I guess that the UARTs on the Intel Galileo board don't use/emulate the normal/legacy COM ports 3F8h, 2F8h, 3E8h, or 2E8h.
Can anyone tell me what I am doing wrong, or even post a minimal bare metal hello world example?
I assume you are aiming at the serial port that is the "audio-like" connector on the Intel Galileo board.
Here are a few resources that should help:
Galileo schematic
Intel Quark SoC X1000 datasheet
Intel Galileo IO Mapping
Sergey's blog entry about Configuring the Serial Port for Galileo
Intel Quark Board Support Package downloads, including
Board Support Package Sources (currently ver.1.0.0)
Intel Quark SoC X1000 UEFI Firmware Writer’s Guide
Things to note about this UART:
This serial port comes out of the QUARK chip as UART1 (see the schematics).
There are a few GPIOs that you may need to manipulate (see Sergey's blog for doing this in Linux):
gpio4: This GPIO controls level shifter for UART signals and some other signals connected to Quark SoC, such as SPI and fast I/O. Writing '1' to this GPIO enables level shifter.
gpio40: This GPIO controls multiplexer for pin 0. Writing '0' to this GPIO connects pin 0 to UART's RxD (receive data) signal.
gpio41: This GPIO controls multiplexer for pin 1. Writing '0' to this GPIO connects pin 1 to UART's TxD (transmit data) signal.
Check the chapter 18 (High Speed UART) in the Quark datasheet for what to put in the UART registers:
Registers DLH, DLL specify the baud rate
Decide whether you want the DMA mode (chapter 18.3.1), the FIFO-interrupt mode (chapter 18.3.2), or the FIFO-polling mode (chapter 18.3.3). The latter is simpler but less effective, IMHO. The former requires you to configure DMA properly as well.
Since there is quite a bit to read for chapter 18 (~67 pages of useful information), I'm not going to retype all that here, please read the datasheet and configure the registers accordingly.
General notes:
For bare-metal approach first make sure that your boot procedure is correct, configuring all the clocking options, GPIO default modes and values, timers if any, etc. For Boot checklist read chapter 4.12 in X1000 UEFI Firmware Writer’s Guide (~18 things to do to boot this chip). After that I'd verify it with a simple "LED blinking" application on a GPIO.
Tinkering with 3F8h and similar ports is not going to help on "bare metal" of this SoC. You need to deal with the registers directly, or find and use appropriate library or framework (maybe UEFI BIOS?).
Programming sources for the particular platform should be a good read for examples.
For example, in Board Support Package Sources for Intel Quark the archive Quark_EDKII_v1.0.0.tar.gz is the UEFI source code for Quark/Galileo. It there, the Serial.c and Serial.h files might just be what you are looking for:
Quark_EDKII_v1.0.0/QuarkSocPkg/QuarkSouthCluster/Uart/Dxe/Serial.*

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