I have the following directory structure. I try to compile all files into object files.
├── Makefile
├── prime_probe.c
└── utils
├── Makefile
├── caches_info.c
├── caches_info.h
├── caches_util.c
├── caches_util.h
├── configure.h
├── list_struct.h
├── list_utils.c
└── list_utils.h
Makefile
THIS_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
OBJDIR = obj
CFLAGS = -I./$(OBJDIR) -g -fPIC -std=gnu99
UTILS_DIR := utils
OBJS_UTL = $(addprefix $(UTILS_DIR)/$(OBJDIR)/,$(notdir $(patsubst %.c,%.o,$(shell find $(UTILS_DIR)/*.c))))
SRCS_PRIME = \
prime_probe.c
OBJS_PRIME = $(addprefix $(OBJDIR)/,$(patsubst %.c,%.o,$(SRCS_PRIME)))
all: clean utils $(OBJS_PRIME)
$(OBJDIR)/%.o: %.c | objdir
$(CC) $(CFLAGS) -c $< -o $(OBJDIR)/$(notdir $#)
utils:
$(MAKE) -C $(UTILS_DIR)
objdir:
#mkdir -p $(OBJDIR)
clean:
rm -rf $(OBJDIR)
$(MAKE) clean -C $(UTILS_DIR)/
The subdirectory Makefile is
THIS_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
##################
# Build directory
##################
OBJDIR = obj
CFLAGS = -I./$(OBJDIR) -g -fPIC -std=gnu99 -static
####################
# Files and folders
####################
SRCS_PRIME = $(shell find ./*.c)
OBJS_PRIME = $(addprefix $(OBJDIR)/,$(patsubst %.c,%.o,$(SRCS_PRIME)))
##########
# Targets
##########
all: $(OBJS_PRIME)
$(OBJDIR)/%.o: %.c | objdir
$(CC) $(CFLAGS) -c $< -g -o $#
objdir:
#mkdir -p $(OBJDIR)
clean:
rm -rf $(OBJDIR)
When I execute the make command, the files in the subdirectory are not compiled.
I do make utils alone and this shows the subdirectories are up to date. But when I enter the subdirectory and execute make, I can see that the file will be compiled.
Why is this so? thanks!!!
root#096b64b8fd50:/usr/local/src/gem5/programs/covert_channel# make
rm -rf obj
make clean -C utils/
make[1]: Entering directory '/usr/local/src/gem5/programs/covert_channel/utils'
rm -rf obj
make[1]: Leaving directory '/usr/local/src/gem5/programs/covert_channel/utils'
cc -I./obj -g -fPIC -std=gnu99 -c prime_probe.c -o obj/prime_probe.o
root#096b64b8fd50:/usr/local/src/gem5/programs/covert_channel# make utils
make: 'utils' is up to date.
root#096b64b8fd50:/usr/local/src/gem5/programs/covert_channel# cd utils/
root#096b64b8fd50:/usr/local/src/gem5/programs/covert_channel/utils# make
cc -I./obj -g -fPIC -std=gnu99 -static -c caches_info.c -g -o obj/./caches_info.o
cc -I./obj -g -fPIC -std=gnu99 -static -c caches_util.c -g -o obj/./caches_util.o
cc -I./obj -g -fPIC -std=gnu99 -static -c list_utils.c -g -o obj/./list_utils.o
If you want build utils as a non-file target then you need to specify it as such with:
.PHONY: utils
I suggest don't use recursive make, besides not providing make with a global state, it also makes it unnecessarily complicated (IMHO).
Related
So, I decided to learn make as my first step into large projects, and I have to say that it is not that hard if you are just doing simple tasks and got addicted to it.
However I usually work with a scheme for my directories:
.
├── build
├── include
│ └── func.h
├── lib
│ └── func.c
├── Makefile
└── src
└── main.c
I usually have all my object files spread in the build directory. However, I could only map the source files to the build folder (like ./build/src/main.o where I prefer ./build/main.o).
I Tried Reading The Documentation to no avail!
this is what I came up with so far:
# C Compiler
CC = gcc
#------------- Directories
SOURCE_DIR = src lib
OBJECTS_DIR = build
INCLUDE_DIR = . ./include
#----------------------------
VPATH = $(SOURCE_DIR)
#------------- Files
SOURCE = $(foreach dir, $(SOURCE_DIR), $(wildcard $(dir)/*.c))
# Fake Objects (Just so I can map them to c files)
FOBJECTS = $(addprefix $(OBJECTS_DIR)/, $(SOURCE:.c=.o))
OBJECTS = $(addprefix $(OBJECTS_DIR)/, $(notdir $(FOBJECTS)))
DEPS = $(foreach dir, $(INCLUDE_DIR), $(wildcard $(dir)/*.h))
#----------------------------
#------------- Flags
OPT = -O0
IFLAGS = $(foreach dir, $(INCLUDE_DIR), -I$(dir))
LFLAGS = -lm
CFLAGS = -Wall
FLAGS = $(OPT) $(IFLAGS) $(LFLAGS) $(CFLAGS)
#----------------------------
BINARY = bin
all : $(BINARY)
$(BINARY) : $(OBJECTS)
$(CC) -o $# $(OBJECTS)
$(OBJECTS) : $(FOBJECTS)
mv -t $(OBJECTS_DIR) $(FOBJECTS)
rm -rf -- $(OBJECTS_DIR)/*/
$(OBJECTS_DIR)/%.o : %.c $(DEPS)
$(CC) $(FLAGS) -c -o $# $<
exec : $(BINARY)
#./$(BINARY)
clean :
rm -rf $(OBJECTS) $(BINARY)
I keep getting this error:
gcc -O0 -I. -I./include -lm -Wall -c -o build/src/main.o src/main.c
Assembler messages:
Fatal error: can't create build/src/main.o: No such file or directory
make: *** [Makefile:39: build/src/main.o] Error 1
I know the reason is the Fake Objects I created but creating the perfect rule for this is hard
As I said, you probably do not want to put all .o in the same directory because comingling .o files from unrelated projects isn't the best organization. If the .o files were related, you'd probably put the .c files in the same subdir.
But, if you did want all .o in a single build directory, one way is to create the build/* subdirs:
# C Compiler
CC = gcc
#------------- Directories
SOURCE_DIR = src lib
OBJECTS_DIR = build
INCLUDE_DIR = . ./include
OBJ_MK = $(addprefix $(OBJECTS_DIR)/, $(SOURCE_DIR))
#----------------------------
VPATH = $(SOURCE_DIR)
#------------- Files
SOURCE = $(foreach dir, $(SOURCE_DIR), $(wildcard $(dir)/*.c))
# Fake Objects (Just so I can map them to c files)
FOBJECTS = $(addprefix $(OBJECTS_DIR)/, $(SOURCE:.c=.o))
OBJECTS = $(addprefix $(OBJECTS_DIR)/, $(notdir $(FOBJECTS)))
DEPS = $(foreach dir, $(INCLUDE_DIR), $(wildcard $(dir)/*.h))
#----------------------------
#------------- Flags
OPT = -O0
IFLAGS = $(foreach dir, $(INCLUDE_DIR), -I$(dir))
LFLAGS = -lm
CFLAGS = -Wall
FLAGS = $(OPT) $(IFLAGS) $(LFLAGS) $(CFLAGS)
#----------------------------
BINARY = bin
all : $(OBJ_MK) $(BINARY)
$(BINARY) : $(OBJECTS)
$(CC) -o $# $(OBJECTS)
$(OBJECTS) : $(FOBJECTS)
mv -t $(OBJECTS_DIR) $(FOBJECTS)
rm -rf -- $(OBJECTS_DIR)/*/
$(OBJECTS_DIR)/%.o : %.c $(DEPS)
$(CC) $(FLAGS) -c -o $# $<
exec : $(BINARY)
#./$(BINARY)
clean :
rm -rf $(OBJECTS) $(BINARY)
rm -rf $(OBJ_MK)
$(OBJ_MK):
mkdir $#
The make output is:
mkdir build/src
mkdir build/lib
gcc -O0 -I. -I./include -lm -Wall -c -o build/src/main.o src/main.c
gcc -O0 -I. -I./include -lm -Wall -c -o build/lib/func.o lib/func.c
mv -t build build/src/main.o build/lib/func.o
rm -rf -- build/*/
gcc -o bin build/main.o build/func.o
However, the above actually makes the build more complex because its "natural" tendency was to create the subdirs. To override that required extra mv and rm commands.
To use the subdirectory method, the build is actually simpler, and we can do:
# C Compiler
CC = gcc
#------------- Directories
SOURCE_DIR = src lib
OBJECTS_DIR = build
INCLUDE_DIR = . ./include
OBJ_MK = $(addprefix $(OBJECTS_DIR)/, $(SOURCE_DIR))
#----------------------------
VPATH = $(SOURCE_DIR)
#------------- Files
SOURCE = $(foreach dir, $(SOURCE_DIR), $(wildcard $(dir)/*.c))
# Fake Objects (Just so I can map them to c files)
OBJECTS = $(addprefix $(OBJECTS_DIR)/, $(SOURCE:.c=.o))
DEPS = $(foreach dir, $(INCLUDE_DIR), $(wildcard $(dir)/*.h))
#----------------------------
#------------- Flags
OPT = -O0
IFLAGS = $(foreach dir, $(INCLUDE_DIR), -I$(dir))
LFLAGS = -lm
CFLAGS = -Wall
FLAGS = $(OPT) $(IFLAGS) $(LFLAGS) $(CFLAGS)
#----------------------------
BINARY = bin
all : $(OBJ_MK) $(BINARY)
$(BINARY) : $(OBJECTS)
$(CC) -o $# $(OBJECTS)
$(OBJECTS_DIR)/%.o : %.c $(DEPS)
$(CC) $(FLAGS) -c -o $# $<
exec : $(BINARY)
#./$(BINARY)
clean :
rm -rf $(OBJECTS) $(BINARY)
rm -rf $(OBJ_MK)
$(OBJ_MK):
mkdir $#
The make output is:
mkdir build/src
mkdir build/lib
gcc -O0 -I. -I./include -lm -Wall -c -o build/src/main.o src/main.c
gcc -O0 -I. -I./include -lm -Wall -c -o build/lib/func.o lib/func.c
gcc -o bin build/src/main.o build/lib/func.o
If you really want all the objects in a single directory, you almost have it right but you added some very strange rules that I don't understand; what is this for:
$(OBJECTS) : $(FOBJECTS)
mv -t $(OBJECTS_DIR) $(FOBJECTS)
rm -rf -- $(OBJECTS_DIR)/*/
? This is what's causing your problem. You're saying that every individual object file depends on all the "intermediate" object files, so then make tries to build these "intermediate" object files. The only way it knows to do that is with the pattern rule you provided, but that doesn't build those files.
Remove that rule altogether and it will probably work. You just want:
VPATH = $(SOURCE_DIR)
OBJECTS = $(addprefix $(OBJECTS_DIR)/, $(notdir $(SOURCE:.c=.o)))
all : $(BINARY)
$(BINARY) : $(OBJECTS)
$(CC) -o $# $(OBJECTS)
$(OBJECTS_DIR)/%.o : %.c $(DEPS)
$(CC) $(FLAGS) -c -o $# $<
etc. The compiler will build the object files directly into their final destination. You don't need the FOBJECTS thing or the rule that uses it.
Everything compile if the C is in outer folder, but when lib.c is in [lib] folder, it gives an error: make: *** No rule to make target 'obj/lib.o', needed by 'run'. Stop.
How should the makefile be corrected to make sure the compilation is successful?
What is the correct way to emend the makefile?
The tree is such:
├── inc
│ └── main.h
├── lib
│ └── lib.c
├── main.c
├── main_functions.sh
├── Makefile
└── test_usages.c
The makefile:
# IDIR =../include \
This is a makefile \
IDIR =./inc
CC=gcc
ODIR=obj
# LIB_SRC_DIR =./lib
LDIR =./lib
CFLAGS=-I $(IDIR) $(LDIR) ## added $(LDIR)
# header files required
_DEPS = *.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
_DEP_LIB = *.c ##
DEPS_LIB = $(patsubst %,$(LDIR)/%,$(_DEP_LIB)) ##
_OBJ = lib.o main.o test_usages.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))
$(ODIR)/%.o: %.c $(DEPS) $(DEPS_LIB) ## added $(DEPS_LIB)
$(CC) -c -o $# $< $(CFLAGS)
#%.o: %.c
# $(CC) $(CFLAGS) $(INCLUDES) -c $(input) -o $(output)
# make commands options: make <options>, e.g. make hello_make
# executable name
hello_make: $(OBJ)
gcc -o $# $^ $(CFLAGS)
run: $(OBJ)
gcc -o $# $^ $(CFLAGS)
echo "=========================================================="
./run
echo "=========================================================="
.PHONY: clean
clean:
echo "cleaning ...." $(ODIR)/*.o
rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~ ./*.exe
Thanks in advance for the advice.
There are some quirks in your Makefile, but here is how I got it to work:
Remove trailing blank in the line LDIR =./lib
Insert VPATH=$(LDIR) at some convenient place
Now make -n run shows (but doesn't run) all expected command lines:
gcc -c -o obj/lib.o ./lib/lib.c -I ./inc ./lib
gcc -c -o obj/main.o main.c -I ./inc ./lib
gcc -c -o obj/test_usages.o test_usages.c -I ./inc ./lib
gcc -o run obj/lib.o obj/main.o obj/test_usages.o -I ./inc ./lib
echo "=========================================================="
./run
echo "=========================================================="
BTW, you could use these options to debug your Makefile:
make -npr run print all variables, rules and so on, but not the built-ins.
make -nd run print all decisions, a lot of them.
I'v written the Makefile below. I'm getting the following error during compilation. I'm not sure what IBS is? Is it missing the L from LIBS or something?
Follow on question:
This is the directory structure.
.
├── Makefile
└── src
├── include
│ └── utils.h
├── main.c
└── utils.c
However, when I run make, this is the output. It doesn't seem to be picking up and building the file utils.c?
cc -I./src -I./src/include -I/usr/local/include/upm -MMD -MP -c
src/main.c -o build/./src/main.c.o.o
TARGET_EXEC ?= app.out
BUILD_DIR ?= ./build
SRC_DIRS ?= ./src
SRCS := $(shell find $(SRC_DIRS) -name *.cpp -or -name *.c -or -name *.s)
OBJS := $(SRCS:%=$(BUILD_DIR)/%.o)
DEPS := $(OBJS:.o=.d)
INC_DIRS := $(shell find $(SRC_DIRS) -type d)
INC_FLAGS := $(addprefix -I,$(INC_DIRS)) -I/usr/local/include/upm
CPPFLAGS ?= $(INC_FLAGS) -MMD -MP
$(BUILD_DIR)/$(TARGET_EXEC): $(OBJS)
$(CC) $(OBJS) -o $# $(LDFLAGS)
LD_FLAGS = -L/usr/local/lib/upm -L/usr/lib/rabbitmq
LIBS = -lrabbitmq -lupmc-rn2483 -lupmc-rn2903 -lupmc-utilities
# c source
$(BUILD_DIR)/%.c.o: %.c
$(MKDIR_P) $(dir $#)
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#.o
$(CC) $(LD_FLAGS) $#.o -o $# $LIBS
.PHONY: clean
clean:
$(RM) -r $(BUILD_DIR)
-include $(DEPS)
MKDIR_P ?= mkdir -p
$(CC) $(LD_FLAGS) $#.o -o $# $LIBS
# wrong ^^^^^
is wrong. Makefile variables need parenthesis: $(LIBS) and your $LIBS is understood as $(L)IBS and you don't have any L variable (so $LIBS expands to IBS since $L expands to nothing)
BTW, you could have used make --trace or remake with -x to find that bug
Regarding the edited question, I believe that you might be wrong in having such a complex source tree for such a small program (generally speaking, small programs of less than a few dozen thousands lines are simpler to deal in a flat source tree, that is a single directory containing both *.c and *.h source files). However, you might consider
INC_DIRS = $(wildcard */include)
I have these files in the same folder:
a.c
b.c
common.c
liba.mk
libb.mk
"liba.mk" is designated to compile "a.c" and "common.c" and archive the object files. "libb.mk" is doing similar works on "b.c" and "common.c"
My problem is, "common.c" appears at both makefile. How to add dependency rules on this? I expect that when I make "liba.mk" and then make "libb.mk", "libb.mk" would re-compile "common.c".
Here is my content on liba.mk:
SRC_C = a.c common.c
SRC_O = $(patsubst %.c,%.o,$(SRC_C))
OBJ_LIST = $(addprefix liba/,$(patsubst %.c,%.o,$(SRC_C)))
DEPENDENCY_LIST = $(addprefix liba/,$(patsubst %.c,%.d,$(SRC_C)))
all: pre_action liba
.PHONY: pre_action
pre_action:
mkdir liba
.PHONY: liba
liba: $(SRC_O)
$(AR) rvs liba/liba.a $(OBJ_LIST)
$(SRC_O): %.o : %.c
$(CC) -DLIBA -c $< -o $#
$(CC) -DLIBA -c $< -MM -MT $# -MF liba/$(patsubst %.o,%.d,$#)
cp $# liba/$(notdir $#)
-include $(DEPENDENCY_LIST)
.PHONY: clean
clean:
rm -rf liba
rm -f $(SRC_O)
And libb.mk has similar content:
SRC_C = b.c common.c
SRC_O = $(patsubst %.c,%.o,$(SRC_C))
OBJ_LIST = $(addprefix libb/,$(patsubst %.c,%.o,$(SRC_C)))
DEPENDENCY_LIST = $(addprefix libb/,$(patsubst %.c,%.d,$(SRC_C)))
all: pre_action libb
.PHONY: pre_action
pre_action:
mkdir libb
.PHONY: libb
libb: $(SRC_O)
$(AR) rvs libb/libb.a $(OBJ_LIST)
$(SRC_O): %.o : %.c
$(CC) -DLIBB -c $< -o $#
$(CC) -DLIBB -c $< -MM -MT $# -MF libb/$(patsubst %.o,%.d,$#)
cp $# libb/$(notdir $#)
-include $(DEPENDENCY_LIST)
.PHONY: clean
clean:
rm -rf libb
rm -f $(SRC_O)
I guess that I need to append extra dependency item when generating dependency file. But it seems silly to perform file processing on dependency file. Is there any better solution for this?
From your comment I now understand that you MUST recompile common.c because it uses different compiler flags (-DLIBB vs. -DLIBA) and, since the dependencies of common.o (i.e. common.c and possibly header files) did not change it did not recompile common.c.
To achieve that you could use:
pre_action:
rm common.o
mkdir libb # or liba
My make is a bit rusty but I believe this will always compile common.c.
I have following folder structure:
TOPDIR
|
├── a
│ ├── a.c
│ ├── a.h
│ └── a.mk
├── b
│ ├── b.c
│ ├── b.h
│ └── b.mk
├── c
│ ├── c.c
│ ├── c.h
│ └── c.mk
├── include
│ └── common.h
├── root
│ ├── main.c
│ └── root.mk
└── Makefile
per-condition
My target is to write main Makefile under TOPDIR and sub-makefile, *.mk in sub folder, the include folder contain some common defines. root folder contain my main file(main function located here). Meanwhile, in main.c, it will call function from a.c and b.c, c.c is driver related, and will be called from a.c and b.c
Problem
I wrote sub-makefile like(I use one a.mk for example, others are same, ONLY root.mk has little different):
#MODULE will be modified for each sub folder
MODULE = a
LIB = $(MAKE_DIR)/libs/lib$(MODULE).a
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c, %.o, $(SRCS))
#generate lib file from obj file
$(LIB): $(OBJS)
#mkdir -p ../libs
#$(AR) cr $# $^
#echo " Archive $(notdir $#)"
#compile obj file from source file
$(OBJS): $(SRCS)
#$(CC) $(CFLAGS) -c $^
#echo " CC $(OBJS)"
.PHONY: clean
clean:
#$(RM) -f $(LIB) $(OBJS)
#$(RM) -f *.expand
#echo " Remove Objects: $(OBJS)"
#echo " Remove Libraries: $(notdir $(LIB))"
I wrote root.mk like:
PROG = ../prog/DEMO
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c, %.o, $(SRCS))
#generate finial target file for run
$(PROG): $(SRCS)
#mkdir -p ../prog
#$(CC) $^ $(CFLAGS) -Wl,-Map=$(PROG).map $(LIBS) -o $#
#echo " Generate Program $(notdir $(PROG)) from $^"
.PHONY: clean
clean:
#$(RM) -f $(OBJS) $(PROG)
#$(RM) -f *.expand
#$(RM) -rf ../prog ../libs
#echo " Remove Objects: $(OBJS)"
#echo " Remove Libraries: $(notdir $(PROG))"
I wrote main Makefile like:
MAKE_DIR = $(PWD)
ROOT_DIR := $(MAKE_DIR)/root
DRV_DIR := $(MAKE_DIR)/driver
INCLUDE_DIR := $(MAKE_DIR)/include
DEBUG_DIR := $(MAKE_DIR)/debug
INC_SRCH_PATH :=
INC_SRCH_PATH += -I$(ROOT_DIR)
INC_SRCH_PATH += -I$(DRV_DIR)
INC_SRCH_PATH += -I$(INCLUDE_DIR)
INC_SRCH_PATH += -I$(DEBUG_DIR)
LIB_SRCH_PATH :=
LIB_SRCH_PATH += -L$(MAKE_DIR)/libs
CC = gcc
LD = ld
#problem happan here, if I change the sequence of LIB,
#during the finial link, it will find some function un-referenced,
#why can I put liba first?
LIBS := -lc -lb -la
CFLAGS :=
CFLAGS += $(INC_SRCH_PATH) $(LIB_SRCH_PATH)
CFLAGS += -Wall -O -ggdb
CFLAGS += -DDEBUG -D_REENTRANT
LDFLAGS :=
export MAKE_DIR CC LD CFLAGS LDFLAGS LIBS LINT INC_SRCH_PATH
all:
#$(MAKE) -C a -f a.mk
#$(MAKE) -C b -f b.mk
#$(MAKE) -C c -f c.mk
#$(MAKE) -C root -f root.mk
.PHONY: clean
clean:
#$(MAKE) -C debug -f debug.mk clean
#$(MAKE) -C driver -f driver.mk clean
#$(MAKE) -C mw -f mw.mk clean
#$(MAKE) -C root -f root.mk clean
Question
In main Makefile, I define which LIB file I will use, if need move it to root.mk for better?
In sub-makefile, I did NOT use -MM to generate depend file, if this cause the problem I can NOT change the sequence of my lib*, which I also described in Makefile comments.
Seems my makefile system can NOT detect I update some head file, for example, I first compiled whole code, and then, I modified one head file, when I try to re-compile, none of source is compiled
if:
#Automatic dependency magic:
%.d: src/%.c
$(CC) -MM -o$# $<
-include (MYPROG_OBJECTS:%.o=%.d)
need add into each sub-makefile?
This rule is definitely wrong:
$(OBJS): $(SRCS)
#$(CC) $(CFLAGS) -c $^
#echo " CC $(OBJS)"
The target line will expand to something like:
a.o b.o c.o d.o : a.c b.c c.c d.c
That's not right. It is identical to writing this:
a.o : a.c b.c c.c d.c
...
b.o : a.c b.c c.c d.c
...
c.o : a.c b.c c.c d.c
...
d.o : a.c b.c c.c d.c
...
This means that whenever you change any source file, ALL the object files will be rebuilt. You should use a pattern rule here:
%.o : %.c
#$(CC) $(CFLAGS) -o $# -c $<
#echo " CC $#"
to compile the object files one at a time.
As far as your questions go, I don't understand question #1.
Questions #2 and #3 (if I understand correctly) are the same thing: the reason for #3 (no files are recompiled when you change a header file) is that you're not declaring any prerequisites on header files. Make doesn't have any built-in support for this, so you either have to do it by hand (add a.o : a.c b.h c.h g.h to your makefiles) or else automatically generate the dependencies.
The dependency generation will typically use the -MM or similar flags, assuming your compiler supports these flags.