I have zero clue what i did wwrong or what im missing. any feedback will be appreciated.
for clarity the error im getting is a vcom 1576 and its near the of it says and it is expecting an identifier.
library ieee;
use ieee.std_logic_1164.all;
entity MCINTOSH_XOR_CASCADE1 is
port(
OP_A: in std_logic_vector(7 downto 0);
OP_Q: out std_logic
);
end MCINTOSH_XOR_CASCADE1;
architecture cascade1_arch of MCINTOSH_XOR_CASCADE1 is
begin
OP_A<= OP_A(0) xor OP_A(1) xor OP_A(2) xor OP_A (3) xor
OP_A(4) xor OP_A(5) xor OP_A(6) xor OP_A(7);
end cascadel_arch;
architecture cascade2_arch of MCINTOSH_XOR_CASCADE1 is
signal p: std_logic_vector (7 downto 0);
begin
p(0) <= OP_A(0);
p(1) <= p(0) xor OP_A(1);
p(2) <= p(1) xor OP_A(2);
p(3) <= p(2) xor OP_A(3);
p(4) <= p(3) xor OP_A(4);
p(5) <= p(4) xor OP_A(5);
p(6) <= p(5) xor OP_A(6);
p(7) <= p(6) xor OP_A(7);
OP_Q <= p(7);
end cascade2_arch;
im doing a project with xors and im trying to put together my entity files to make a test bench
Related
I am converting an old AHDL code to VHDL, and I need to create 5 arrays of resisters using a generate statement. I've never used generate before, and after trying for a couple of hours I still can't find an answer for my problem. My initial approach was to use a 18 bit input array, and a 18 bit output array, but I know that that's not the way to do it.
This is the code I have right now:
entity setup_comp_reg is
generic(
NUM_ID: integer := 18
);
port (
clk: in std_logic;
D: in std_logic_vector(17 downto 0);
clrn: in std_logic;
ena: in std_logic;
Q: out std_logic_vector(17 downto 0)
);
end setup_comp_reg;
architecture rtl of setup_comp_reg is
begin
DFFE: process (clk, clrn, ena) -- 18 times, using generate
begin
if (clrn = '0') then
Q<= (others => '0');
elsif (rising_edge(clk)) then
if (ena = '1') then
Q<= D;
end if;
end if;
end process;
end rtl;
So, I already have the DFFE, but how to use generate to create 5 arrays with 18 bits each?
The AHDL code is pretty self explanatory, it might help too:
for i in 17 to 0 generate
rg_bit_time[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adBT&iWR);
rg_sample_time[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adSP&iWR);
rg_low_sync[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adLS&iWR);
rg_hi_sync[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adHS&iWR);
end generate;
Thank you.
The AHDL generate statement represents four flip flops for each iteration of i.
AHDL generate statement:
for i in 17 to 0 generate
rg_bit_time[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adBT&iWR);
rg_sample_time[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adSP&iWR);
rg_low_sync[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adLS&iWR);
rg_hi_sync[i].(d, clk, clrn, ena) = (iDATA[i], clk, not reg_reset, adHS&iWR);
end generate;
AHDL uses a function prototype to represent primitives (here, DFFE). The return value would be the q output (and isn't mentioned in the AHDL generate statement). There are four assignments to names with function prototype associations. That represents four arrays of 18 flip flops.
The function prototype for the DFFE register is shown in the Altera Hardware Description Language (AHDL) Language Reference Manual, Section 3, Primitives, Flip Flop and latch Primitives, Table 3-9. MAX+PLUS II Flipflops & Latches:
Where the return value would be associated with the name (e.g. rg_bit_time[i]) in assignment statements in the AHDL generate statement.
In VHDL we'd do that by associating actuals with formals of a DFFE entity that would include the output.
A behavioral representation with ports for all the outputs and inputs would look something like:
library ieee; -- ADDED context clause
use ieee.std_logic_1164.all;
entity setup_comp_reg is
generic (
NUM_ID: integer := 18
);
port (
clk: in std_logic;
D: in std_logic_vector(NUM_ID - 1 downto 0);
clrn: in std_logic;
ena: in std_logic;
-- Q: out std_logic_vector(17 downto 0)
WR: in std_logic; -- ADDED
adBT: in std_logic; -- ADDED
adSP: in std_logic; -- ADDED
adLS: in std_logic; -- ADDED
adHS: in std_logic; -- ADDED
rg_bit_time: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_sample_time: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_low_sync: out std_logic_vector(NUM_ID - 1 downto 0); -- ADDED
rg_hi_sync: out std_logic_vector(NUM_ID - 1 downto 0) -- ADDED
);
end entity setup_comp_reg;
architecture rtl of setup_comp_reg is
-- For no -2008 dependency, ADD these:
signal adBTWR: std_logic;
signal adSPWR: std_logic;
signal adLSWR: std_logic;
signal adHSWR: std_logic;
begin
-- Write ENABLE conditions:
adBTWR <= adBT and WR;
adSPWR <= adSP and WR;
adLSWR <= adLS and WR;
adHSWR <= adHS and WR;
SETUP_REGS:
for i in NUM_ID - 1 downto 0 generate
BIT_TIME:
process (clk, clrn) -- enables not needed in sensitivity list
begin
if clrn = '0' then
rg_bit_time(i) <= '0';
elsif rising_edge (clk) then
if adBTWR = '1' then
rg_bit_time(i) <= D(i);
end if;
end if;
end process;
SAMPLE_TIME:
process (clk, clrn)
begin
if clrn = '0' then
rg_sample_time(i) <= '0';
elsif rising_edge (clk) then
if adSPWR = '1' then
rg_sample_time(i) <= D(i);
end if;
end if;
end process;
LOW_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_low_sync(i) <= '0';
elsif rising_edge (clk) then
if adLSWR = '1' then
rg_low_sync(i) <= D(i);
end if;
end if;
end process;
HI_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_hi_sync(i) <= '0';
elsif rising_edge (clk) then
if adHSWR = '1' then
rg_hi_sync(i) <= D(i);
end if;
end if;
end process;
end generate;
end architecture rtl;
You could associate individual flip flops from an entity (DFFE) but there's no need in a VHDL Register Transfer Logic (RTL) representation. In AHDL you'd have no choice, a named element would be a flip flop associated more than likely with a pin of a device.
You could also streamline the above description, it's written this way to show providence with the AHDL generate statement (without individual flip flops).
Using a generate statement with instantiated flip flops would elaborate to i number of nested block statements for the instantiation, the outer for the port map, the inner containing one or more processes implementing the flip flop for each of the four names. The above does that without instantiation (saving one block statement nesting level).
A description using loop statements instead of the generate statement would eliminate all the processes for individual flip flops and could be collapsed further by using assignment with a target that's an array object:
architecture rtl1 of setup_comp_reg is
-- For no -2008 dependency, ADD these:
signal adBTWR: std_logic;
signal adSPWR: std_logic;
signal adLSWR: std_logic;
signal adHSWR: std_logic;
begin
-- Write ENABLE conditions:
adBTWR <= adBT and WR;
adSPWR <= adSP and WR;
adLSWR <= adLS and WR;
adHSWR <= adHS and WR;
-- SETUP_REGS:
BIT_TIME:
process (clk, clrn) -- enables not needed in sensitivity list
begin
if clrn = '0' then
rg_bit_time <= (others => '0');
elsif rising_edge (clk) then
if adBTWR = '1' then
rg_bit_time <= D;
end if;
end if;
end process;
SAMPLE_TIME:
process (clk, clrn)
begin
if clrn = '0' then
rg_sample_time <= (others => '0');
elsif rising_edge (clk) then
if adSPWR = '1' then
rg_sample_time <= D;
end if;
end if;
end process;
LOW_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_low_sync <= (others => '0');
elsif rising_edge (clk) then
if adLSWR = '1' then
rg_low_sync <= D;
end if;
end if;
end process;
HI_SYNC:
process (clk, clrn)
begin
if clrn = '0' then
rg_hi_sync <= (others => '0');
elsif rising_edge (clk) then
if adHSWR = '1' then
rg_hi_sync <= D;
end if;
end if;
end process;
end architecture rtl1;
That's four process statements.
The canny ready will notice the code could be compacted further by using separate enables for the named register outputs:
architecture rtl2 of setup_comp_reg is
signal adBTWR: std_logic;
signal adSPWR: std_logic;
signal adLSWR: std_logic;
signal adHSWR: std_logic;
begin
-- Write ENABLE conditions:
adBTWR <= adBT and WR;
adSPWR <= adSP and WR;
adLSWR <= adLS and WR;
adHSWR <= adHS and WR;
BT_SP_LS_HS:
process (clk, clrn) -- enables not needed in sensitivity list
begin
if clrn = '0' then
rg_bit_time <= (others => '0');
rg_sample_time <= (others => '0');
rg_low_sync <= (others => '0');
rg_hi_sync <= (others => '0');
elsif rising_edge (clk) then
if adBTWR = '1' then
rg_bit_time <= D;
end if;
if adSPWR = '1' then
rg_sample_time <= D;
end if;
if adLSWR = '1' then
rg_low_sync <= D;
end if;
if adHSWR = '1' then
rg_hi_sync <= D;
end if;
end if;
end process;
end architecture rtl2;
Process statements are the unit of simulation in VHDL. The fewer there are the less execution overhead from suspension and resumption. The rtl2 example has one process statement. It works without having all the enables in the sensitivity list because they are 'sampled' on the clock rising edge. The authority for leaving the enables out comes from IEEE Std 1076.6-2004 (now withdrawn, RTL Synthesis) which describes syntax for and the required sensitivity list elements for edge sensitive sequential logic. Vendors typically provide examples of a subset of the sequential logic forms they will support and are guaranteed to comply with 1076.6.
The VHDL code above all analyzes.
(Looks like part of an IC tester.)
I'm a newbie user of VHDL.
I have an error in this code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AandB is
Port ( a : in STD_LOGIC_vector(31 downto 0);
b : in STD_LOGIC_vector(31 downto 0);
salida : out STD_LOGIC_vector(31 downto 0)
);
end AandB;
architecture Behavioral of AandB is
begin
for i in 0 to 31 loop
salida(i) <= a(i) and b(i);
end loop;
end Behavioral;
the error is this:
ERROR:HDLCompiler:806 - Line 43: Syntax error near "for".
ERROR:HDLCompiler:69 - Line 45: <i> is not declared.
ERROR:HDLCompiler:806 - Line 47: Syntax error near "generate".
ERROR:HDLCompiler:854 - Line 39: Unit <behavioral> ignored due to previous errors.
I have searched for the enter code here`first 3 errors. Haven't noticed what is the syntax error for the "for" statement; It's supposed that is indirectly declared within the loop; Don't know about the error in "generate".
Some help?
ThirtyTwoAnd: for i in 0 to 31 generate
salida(i) <= a(i) and b(i);
end generate ThirtyTwoAnd;
What Jim said can even be simplified. ieee.std_logic_1164 actually defines:
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector;
So you could in this case of equal length vectors just write:
salida <= "and"(a, b);
But just this will also work:
salida <= a and b;
I'm doing a musicbox with VHDL. I first played just A4 and I was successful.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Basic is
Port( clk : in STD_LOGIC;
note : out STD_LOGIC;
);
end Basic;
architecture Behavioral of Basic is
signal count : unsigned (15 downto 0) := (others => '0');
begin
note <= std_logic(count(15));
process (clk)
begin
if rising_edge(clk) then
if (count=56817) then
count <= "0000000000000000";
else
count <= count + 1;
end if;
end if;
end process;
end Behavioral;
My unfinished code is like this
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Basic is
Port( clk : in STD_LOGIC;
note : out STD_LOGIC;
address: in integer range 0 to 31
);
end Basic;
architecture Behavioral of Basic is
signal count : unsigned (15 downto 0) := (others => '0');
signal reg_address : integer range 0 to 31 ;
type rom_array is array (0 to 31) of integer (4 downto 0);
constant rom: rom_array := ( "11011", "11011",
"11011", "11011","11011", "11011",
"11011", "11011", "11011", "11011",
"11011", "11011","11011", "11011",
"11011", "11011","11011", "11011",
"11011", "11011","11011", "11011",
"11011", "11011","11011", "11011",
"11011", "11011","11011", "11011",
"11011", "11011");
begin
note <= std_logic(count(15));
process (clk)
begin
if rising_edge(clk) then
reg_address <= address;
if (reg_address < 32) then
if (count = rom(reg_address)) then
count <= "0000000000000000";
else
count <= count + 1;
end if;
else
reg_address <= "00000";
end if;
end if;
reg_address <= reg_address + 1;
end process;
end Behavioral;
the rom values are going to change.
I'm trying to generate a sound by dividing the clock. Like 25mhz/56818 = 440. To play a song I thought of creating a rom filled with numbers needed to divide the clock, then do a for loop and play the song. But I can't because for loop isn't similar to java/C so I think I need to bypass it.
My errors are:
ERROR:HDLParsers:526 - "C:/Users/user/DigitalProje/Basic.vhd" Line 18. Non array type integer can not have a index constraint.
ERROR:HDLParsers:3312 - "C:/Users/user/DigitalProje/Basic.vhd" Line 19. Undefined symbol 'rom_array'.
ERROR:HDLParsers:1209 - "C:/Users/user/DigitalProje/Basic.vhd" Line 19. rom_array: Undefined symbol (last report in this block)
ERROR:HDLParsers:3285 - "C:/Users/user/DigitalProje/Basic.vhd" Line 19. No array or record type can be found that has elements of types matching the aggregate.
ERROR:HDLParsers:532 - "C:/Users/user/DigitalProje/Basic.vhd" Line 19. Deferred constant are allowed only in packages.
ERROR:HDLParsers:808 - "C:/Users/user/DigitalProje/Basic.vhd" Line 35. = can not have such operands in this context.
ERROR:HDLParsers:800 - "C:/Users/user/DigitalProje/Basic.vhd" Line 41. Type of reg_address is incompatible with type of 00000.
VHDL is a strong-typed language, so you must be strict with the types.
Two issues, the rom_array is made with integer type elements, but it looks like the intention may have been to use unsigned (or another vector type) based on the constant assign to rom; so maybe do:
type rom_array is array (0 to 31) of unsigned (4 downto 0);
The reg_address is integer, thus it can't be assigned with string like in reg_address <= "00000";, so consider changing this to:
reg_address <= 0;
I have a vector A that's 64bits long and I want the output B to equal 3 while A is 30-35 and zero elsewhere. I can't figure out the testbench to loop through the vector A as a bit. I've tried several different ways but only got 1/5 of the array to give any output at all. This is as far as I could get without syntax/compile errors.
Main code
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity ent is
port(A:in std_logic_vector(5 downto 0);
B:out std_logic_vector(3 downto 0));
end ent;
architecture arch_ent of ent is
begin
with A select
B <= "0011" when "011110",
"0011" when "011111",
"0011" when "100000",
"0011" when "100001",
"0011" when "100010",
"0011" when "100011",
"0000" when others;
end arch_ent;
Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end tb;
architecture arch_tb of tb is
component ent
port(A:in std_logic_vector(5 downto 0);
B:out std_logic_vector(3 downto 0));
end component;
signal A_tb: std_logic_vector(5 downto 0);
signal B_tb: std_logic_vector(3 downto 0);
begin
uut: entity ent port map(A=>A_tb, B=>B_tb);
tb: process
constant period: time := 20ns;
begin
for i in A_tb'range loop
A_tb <= std_logic_vector(to_unsigned(i,6));
wait for period;
assert (B_tb = "0011")
report "test failed" severity error;
end loop;
wait;
end process;
end arch_tb;
In the end I'm trying to plot out the waveform like this:
http://i10.photobucket.com/albums/a142/blargonblop/wave.png
where A will go to 63 and each output is its correct value from 30-35 and 0 elsewhere
The loop parameter you use to specify the number of 'tests' is A_tb'range, which happens to be 5 downto 0, or six tests, i is assigned 5,4,3,2,1 and 0 successively.
You want to specify i in 0 to 2**A-tb'length-1 or i in 0 to 63 to get all 64 possible A_tb 'binary' values.
(A_tb'length = 6, 2**6-1 = 63, where ** is the exponentiation operator, 2 to the 6th power minus 1 equals 63)
I found two syntax errors in your test bench, 20ns where the standard requires a space between 20 and ns:
constant period: time := 20 ns;
And entity ent where that should either be just ent (you have a component declaration ent) or entity work.ent and no need for a component declaration:
uut: ent port map(A=>A_tb, B=>B_tb);
or
uut: entity work.ent port map(A=>A_tb, B=>B_tb);
And in keeping with Russell's answer there is no implied logic replication in a loop other than through synthesis which unravels loop iterations by paralleling logic (the replication). Not all loop statements are intended as synthesis targets.
Test benches are generally not synthesized and are used to write tests (as in your case) for a VHDL model that might be used as a synthesis target.
First, loops are just fine, and common, in testbenches. #Russell's comment applies to RTL code. You can adapt his approach for this problem and make it work. You would need to use 64 as a sentinel (ending) value and do your end of test checks then. Keep in mind though that the most important thing you do is code for readability. Test cases generally run from top to bottom of a process one time.
You loop has some issues in addition to the recommendations #DavidKoontz gave. Specifically,
Your assertion is should not be checked when you expect B to be 0.
Using numeric_std_unsigned (requires VHDL-2008 compile switch) will simplify your conversions.
Keep an error count so you can report pass or failed at the end.
Keep your constants in the architecture or a package
So the modified code is:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
entity tb is
end tb;
architecture arch_tb of tb is
constant period: time := 20 ns;
...
begin
...
tb: process
variable ErrorCount :
begin
for i in i in 0 to 2**A-tb'length-1
A_tb <= to_slv(i,6);
wait for period;
if i >= 30 and i <= 35 then
if B_tb /= 3 then
ErrorCount := Error Count + 1 ;
report "B_tb = " & to_string(B_tb) & " Expecting: 0011" severity ERROR ;
end if;
else
if B_tb /= 0 then
ErrorCount := Error Count + 1 ;
report "B_tb = " & to_string(B_tb) & " Expecting: 0000" severity ERROR ;
end if;
end loop;
if ErrorCount = 0 then
report "Test Passed" severity NOTE ;
else
report "Test FAILED. There were " & to_string(ErrorCount) & " Errors " severity NOTE;
end if;
std.env.stop(0) ; -- testbench stops here
end process;
Note that the rules about using (or forbidding usage of) numeric_std_unsigned do not apply to testbenches.
You really should not be using a for loop for this. For loops in VHDL are used to REPLICATE LOGIC, not to do something some number of times. Try something like this in your test bench:
signal r_CLOCK : std_logic := '0';
signal r_INDEX : unsigned(5 downto 0) := (others => '0');
begin
r_CLOCK <= not r_CLOCK after period/2;
process (r_CLOCK)
begin
if rising_edge(r_CLOCK) then
r_INDEX <= r_INDEX + 1;
end if;
end process;
Now simply cast r_INDEX as std_logic_vector and pass it to your ent component.
How do you concatenate bits in VHDL? I'm trying to use the following code:
Case b0 & b1 & b2 & b3 is
...
and it throws an error
Thanks
The concatenation operator '&' is allowed on the right side of the signal assignment operator '<=', only
You are not allowed to use the concatenation operator with the case statement. One possible solution is to use a variable within the process:
process(b0,b1,b2,b3)
variable bcat : std_logic_vector(0 to 3);
begin
bcat := b0 & b1 & b2 & b3;
case bcat is
when "0000" => x <= 1;
when others => x <= 2;
end case;
end process;
Here is an example of concatenation operator:
architecture EXAMPLE of CONCATENATION is
signal Z_BUS : bit_vector (3 downto 0);
signal A_BIT, B_BIT, C_BIT, D_BIT : bit;
begin
Z_BUS <= A_BIT & B_BIT & C_BIT & D_BIT;
end EXAMPLE;