Error: *** No rule to make target 'Home' Stop
There how I wrote my Makefile:
obj-m += hello-1.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
The problem is with your folder naming, instead naming the folder OS Home Assignment, name it with underlines os_home_assigmnet.
more details can be found here
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I am working on a simple driver for a class. I am using this makefile:
obj-m := mysourcefile.o
KERNELDIR ?= /lib/modules/$(shell uname -r)/kernel
all default: modules
install: modules_install
modules modules_install help clean:
$(MAKE) -C $(KERNELDIR) M=$(pwd) $#
When I run this using the line:
make
I get the error:
no rule to make target 'modules'. Stop.
I do want to note, my textbook suggests this line:
KERNELDIR ?= /lib/modules/$(shell uname -r)/build
However, I have no "build" directory in my version of Debian (10.6.0-3) (Kernel v. 4.19.0-10-amd64), so I changed the file to point to kernel, since I believe the makefile is supposed to point to the kernel. I don't know if this was the correct choice or not. My active directory IS the directory which contains my source code.
I am unsure of how to proceed from this point.
I have installed Ubuntu on a VMWare. My purpose is to build kernel modules in it. I am a beginner. I have written a basic module. But I am not able to compile it with the 'Makefile'. What do I need to fix?
Contents of the C file(kernel.c):-
#include <linux/kernel.h>
MODULE_LICENSE("GPL");
Contents of the makefile:-
obj-m+=kernel.o
all:
make -C /lib/modules/$(shell uname -r)/build/ M=$(shell PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(shell PWD) clean
Make uses TAB as delimiter, not space. Your Makefile should be written as below.
obj-m+=kernel.o
all:
make -C /lib/modules/$(shell uname -r)/build/ M=${PWD} modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=${PWD} clean
It should also be noted that ${PWD} is an environment variable. There is no need to shell out to read an env variable.
I'm trying to compile a simple hello world module following this guide and I'm confused about what the Makefile is actually doing.
obj-m += hello-1.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
I understand that when i type the make command it will run the all recipe which runs make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules. So now it runs the Makefile found at the path given after the -C flag but what does the M=$(PWD) modules do?
'obj-m' :- specifies object files which are built as loadable
kernel modules.
'all and clean' :- If you run 'make' by default it will run "all :".
But we can use all and clean with make. it will run only those specific command.
Example :-
'make all' will run "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules"
'make clean will run "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean"
3.'uname -r' :- get name and information about current kernel.
Example :- for me, my kernel is "4.6.0-rc1".
Option ‘-C dir’ :- Change to directory dir before reading the makefiles.
Example :- "make -C /lib/modules/$(shell uname -r)/build" will change to "make -C /lib/modules/4.6.0-rc1/build.
'$pwd':- get the path of your current directory.
Now you want to create your loadable module by using "make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules".
Your source code need environment to run. That's why we have to use -C option to change build directory. Which have all needed definition, header file, Macro and etc. Now after changing to build directory you need to tell where is your module present, that's why we are using M=$PWD.
To compile kernel module, the make command you normally need is in this form:
make -C /lib/modules/3.16.0-70-generic/build M=/home/test/ldd3/hello modules
in which, -C means switching to another path.
/lib/modules/3.16.0-70-generic/
is the path to the kernel in used, and
/home/test/ldd3/hello
is where the source of your module resides.
what does the M=$(PWD) modules do?
So as I said M=$(PWD) is simply a shell variable that stores the current path to your kernel module. make needs to store this as it switches to the kernel build path.
Below are the details of my test project
myproject/
|
|- Makefile1
|- test_module.c
|- test/
|- Makefile2
Below are the contents of my make files
Makefile 1:
obj-m:=test_module.o
all:
$(MAKE) -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) modules;
clean:
$(MAKE) -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) clean;
Makefile2:
obj-m:=../test_module.o
all:
$(MAKE) -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) modules;
clean:
$(MAKE) -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) clean;
When i invoke make in the myproject directory, test_module.o is getting compiled. If i cd to the test/ directory and invoke make, again test_module.o is getting compiled. That is not my expected behavior. Make should not compile test_module.o again since it is already compiled. It should use that object file to generate corresponding executable or kernel module. Do i miss any thing here?
Yes, in the Linux kernel build system object files are not reused for different targets(e.g., kernel modules).
This is caused by auxiliary build files, stored alongside with objects files. E.g., in you case .test_module.o.cmd uses exact path to test_module.o. When file is created by Makefile1, this path ends with test_module.o, but when Makefile2 is in question, path ends with test/../test_module.o.
The functions you write to provide procfs interfaces is just code that is part of your LKM source.
http://linux.die.net/lkmpg/x769.html has a simple example using procfs, reproduced here:
I copied the code from above link -
You'll find a tutorial for building kernel modules at http://www.cyberciti.biz/tips/compiling-linux-kernel-module.html. The summary of that is:
1) Ensure you have kernel source installed in /usr/src.
2) Create a makefile that looks like:
obj-m = procfs2.o
KVERSION = $(shell uname -r)
all:
make -C /lib/modules/$(KVERSION)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(KVERSION)/build M=$(PWD) clean
3) build the module with the command make 4) load the module into memory with the command insmod procfs2.ko (do this as the root user)
I copied the code and created the MAKEFILE and later if I give the make command from the console then it is showing as : make: nothing to be done for all. could someone please tell me what could be the error ??
Here is an example of a Makefile for a kernel module.
the important thing here to note is that the dots shown below must be replaced by a TAB, replacing them by spaces will cause Makefile to malfunction.
obj-m += hello.o
all:
.......make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
.......make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean