issue in counting down timer from 60 to 0 on 7segment - c

Question

/*
T=1/8MHz=0.125us
0>>>256=32us time for 1 clock
1/32*(10^-6)
so we need 31250 clock to generate 1 sec
for prescaling 256 we need 123 clock
*/
/*
123 CLOCK FOR 1 SEC
SO 1230 CLOCK FOR 10 SEC
*/
#define F_CPU 8000000UL
#include <avr/io.h>
void T0delay()
{
TCNT0 = 0;
TCCR0 = 0x04;
while (TIFR & (1<<TOV0)==0);
TCNT0 = 0;
TIFR =0x01;
}
int main(void)
{
int counter=0;
int i=0;
int j=6;
DDRC=0xff;
DDRD=0xff;
PORTC=i;
PORTD=j;
while (1)
{
T0delay();
counter++ ;
if(counter == 123)
{
i--;
if(i < 0)
{
i = 9;
PORTD--;
if(PORTD == 0 & PORTC == 0 )
{
PORTD =0;
PORTC =0;
}
}
PORTC=i;
}
}
}
Port c for stepping down timer from 9 to 0 count each sec.
Behavior is not accurate as it doesn't wait whole second.
While port d for stepping down timer from 6 to 0 count each cycle (9 to 0 ) of the port c 7segment.
The behavior is not right as it counts from 6 to 0 then it displays unwanted segments.
Schematics

Answer 1

To solve your problem, you need to analyze the different cases for the values that you are branching on (if statements) and how you are treating their values.
First off, PORTD and PORTC are GPIO registers which means their values are unsigned so I believe the problem with your code is right here:
PORTD--;
if(PORTD == 0 & PORTC == 0 )
{
PORTD =0;
PORTC =0;
}
When the if(PORTD == 0 & PORTC == 0 ) branch is taken, PORTD is set to 0. The next time if(i < 0) is taken PORTD is then decremented which causes overflow, giving you the unwanted behavior you are experiencing.