As the title impplies, I've ATMEGA64a-au and 12mhz crystal, I set the baud rate to 9600 by these codes:
#define F_CPU 12000000UL
#define FOSC 12000000 // Clock Speed
#define BAUD 9600
#define MYUBRR FOSC/16/BAUD-1
..
void USART0_Init( unsigned int ubrr )
{
UBRR0H = (unsigned char) (ubrr >> 8);
UBRR0L = (unsigned char) ubrr;
UCSR0B = (1 << RXEN0) | (1 << TXEN0) | (1 << RXCIE0);
// Set frame format: 8data, 1stop bit
UCSR0C = (1 << USBS0) | (3 << UCSZ00);
}
void USART1_Init( unsigned int ubrr )
{
UBRR1H = (unsigned char) (ubrr >> 8);
UBRR1L = (unsigned char) ubrr;
UCSR1B = (1 << RXEN1) | (1 << TXEN1) | (1 << RXCIE1);
// Set frame format: 8data, 1stop bit
UCSR1C = (1 << USBS1) | (3 << UCSZ10);
}
..
USART0_Init(MYUBRR);
USART1_Init(MYUBRR);
It is fine when I work with that baud rate but I've recently come a cross a 115200bd device and I need too change it to that, but when I change this line :
#define BAUD 115200
The AVR Micro controller stops communicating, and I've no idea how to fix it. is it too fast for that device or I'm missing something?
#define MYUBRR FOSC/16/BAUD-1
First of all there is an issue with this formula: it rounds always downwards. You need to round it to near integer, e.g. (FOSC / 16 + BAUD / 2) / BAUD-1
By the way why it is FOSC and not F_CPU?
Anyway, you can calculate the error when formula FOSC/16/BAUD-1 is used:
MYUBRR = 12000000/16/115200-1 = 5 (5.51 rounded downwards)
Actual UART speed will be:
F_CPU / 16 / (MYUBRR + 1) = 12000000 / 16 / (5 + 1) = 125000
which is 8.5% higher than required. Communication with receiver-transmitter baud rate difference more than 4.5% is not possible.
But you can set Double Speed Operation mode (refer to section 25.3.2 of the datasheet)
It can be done by setting bit U2X bit in UCSRA.
In that case UART clock will be 1/8 of the CPU clock, thus allowing higher UBRR settings:
// divide by 8, not 16
#define MYUBRR ((FOSC / 8 + BAUD / 2) / BAUD - 1)
...
void USART0_Init( unsigned int ubrr )
{
// you can just assign the value to UBRR, compiler will handle all the thighs
UBRR0 = ubrr;
UCSR0A = (1 << U2X0); // enable 2x mode
UCSR0B = (1 << RXEN0) | (1 << TXEN0) | (1 << RXCIE0);
// Set frame format: 8data, 1stop bit
UCSR0C = (1 << USBS0) | (3 << UCSZ00);
}
In this case MYUBRR value will be:
(12000000 / 8 + 115200 / 2) / 115200 - 1 = 12
and actual UART speed will be
12000000 / 8 / (12 + 1) = 115384,6
which gives you less than 0.2% error
I have a function as follows:
union u_t
{
uint16_t u16;
uint8_t u8[2];
};
uint16_t Frame2Data(uint8_t *data,uint8_t startBit,uint16_t length)
{
uint16_t mask;
uint8_t start;
uint8_t firstByte,offset;
uint8_t numShift;
union u_t ut;
for(i=0;i<16;i++)
{
if(length == i)
mask|=(1<<i);
}
firstByte = startBit / 8;
offset = (firstByte+2) * 8;
start = startBit + length;
numShift = offset - start;
ut.u8[1] = data[firstByte];
ut.u8[0] = data[firstByte+1];
return (ut.u16 >> numShift) & mask;
}
The start bit is 46 and length is 7 and the data in 8 bytes is 0x00 0x09 0x03 0x84 0x03 0x70 0x02 0xA8 has to be passed. I have to extract the data with start bit 46 and upto a length of 7 bits and find out its value. I have a doubt with numbershift and is my function working correctly? It would be great if someone confirms this.Thanks in advance.
Your problem here, is the way in which you set your mask:
for(i=0;i<16;i++)
{
if(length == i)
mask|=(1<<i); /* BTW, mask is not initialized */
}
is simply equivalent to:
mask |= (1 << length);
which will set only one bit in you mask. So either you substruct one from mask after the for, or you set it directly:
#define UINT16_WIDTH 16
mask = (1u << (length & (UINT16_WIDTH - 1))) - 1u;
Thanks in advance for any help anyone can provide!
Here is my issue: I am replacing an obsolete LCD. Both LCDs, new and old, are 240 wide by 128 tall pixels, but have different pixel arrangements.
I have written code to translate the Screen array from the OLD to the NEW format, but it is too slow. I am hoping someone better at bit manipulation that me can come up with a better method. Below is an arrangement as arrows that represent a byte of 8 pixels and what their orientation is on the LCD.
Basically the old LCD is arranged in 8 pixel bytes in horizontal slices that increment horizontally and wrap around then increment vertically.
The new LCD is arranged in 8 pixel bytes in vertical slices that increment horizontally and wrap around then increment vertically.
I am trying to visualize both arrangements with arrows representing the 8 pixel bytes as vertical or horizontal arrows pointing in the direction the bits increment. Each arrow in both representations is one byte or 8 pixels.
Here is the old LCD’s arrangement: 30 bytes by 128 bytes for 30,720 bits or pixels
240 bits horizontal is 30 bytes
128 bytes vertical
Old LCD
Here is the new LCD’s arrangement: 240 bytes by 16 bytes for 30,720 bits or pixels
128 bits vertical in 16 bytes
240 bytes horizontal
New LCD
Below is my translation code that WORKS, but is too slow. It increments through the bytes of the new arrangement, finding where each bit for each byte from the old arrangement came from. Too slow and tedious, lagging the system, there must be a better way! I tried changing all function calls to inline code with no improvement.
#define DISPLAY_BUFFER_SIZE 3840 // buffer size in *bytes*
#define HORIZONTAL_PIX 240
#define VERTICAL_ROWS 16
#define VERTICAL_PIX 128
#define HORIZONTAL_COL 30
#define BITS_IN_BYTE 8
UBYTE isBitSet(UBYTE* arr, USHORT bit)
{
USHORT index = bit / 8; // Get the index of the array for byte with this bit
USHORT bitPosition = 7-(bit % 8); // Position of this bit a byte Every byte on the OLD LCD was bit swapped from MSB to LSB so annoyingly this is reversed here
return (arr[index] >> bitPosition & 1) == 1;
}
// main code inside another function
for (i=0; i<DISPLAY_BUFFER_SIZE; i++)
{
newbyte_pos = i % HORIZONTAL_PIX; // Value is 0 to 29. 30 = 240col / 8bits
newbyte_offset = i / HORIZONTAL_PIX; // Value is 0 to 127
new_display_byte = 0x00;
// Bit 0
oldbit_num = (newbyte_offset * 1920) + (240 * 0) + newbyte_pos;
if (isBitSet(buffer_pointer, oldbit_num))
new_display_byte |= 0x01;
// Bit 1
oldbit_num = (newbyte_offset * 1920) + (240 * 1) + newbyte_pos;
if (isBitSet(buffer_pointer, oldbit_num))
new_display_byte |= 0x02;
// Bit 2
oldbit_num = (newbyte_offset * 1920) + (240 * 2) + newbyte_pos;
if (isBitSet(buffer_pointer, oldbit_num))
new_display_byte |= 0x04;
// Bit 3
oldbit_num = (newbyte_offset * 1920) + (240 * 3) + newbyte_pos;
if (isBitSet(buffer_pointer, oldbit_num))
new_display_byte |= 0x08;
// Bit 4
oldbit_num = (newbyte_offset * 1920) + (240 * 4) + newbyte_pos;
if (isBitSet(buffer_pointer, oldbit_num))
new_display_byte |= 0x10;
// Bit 5
oldbit_num = (newbyte_offset * 1920) + (240 * 5) + newbyte_pos;
if (isBitSet(buffer_pointer, oldbit_num))
new_display_byte |= 0x20;
// Bit 6
oldbit_num = (newbyte_offset * 1920) + (240 * 6) + newbyte_pos;
if (isBitSet(buffer_pointer, oldbit_num))
new_display_byte |= 0x40;
// Bit 7
oldbit_num = (newbyte_offset * 1920) + (240 * 7) + newbyte_pos;
if (isBitSet(buffer_pointer, oldbit_num))
new_display_byte |= 0x80;
new_display_buf[i] = new_display_byte;
}
}
Here is the new code based on the very helpful suggestion from Mark Ransom:
void transpose8x8bits(UBYTE * block, UBYTE * result)
{
int bit;
for (bit = 7; bit >= 0; bit--)
{
result[7-bit] = (((block[0] >> bit) & 1) << 0) |
(((block[30] >> bit) & 1) << 1) |
(((block[60] >> bit) & 1) << 2) |
(((block[90] >> bit) & 1) << 3) |
(((block[120] >> bit) & 1) << 4) |
(((block[150] >> bit) & 1) << 5) |
(((block[180] >> bit) & 1) << 6) |
(((block[210] >> bit) & 1) << 7);
}
}
//////////////////////////////////////////////////////////////////
// calling code
buf_inx = 0;
for (z=0; z<16; z++) // 128 bits / 8 bit per byte = 16 bytes
{
for (i=0; i<30; i++)
{
transpose8x8bits((buffer_pointer+i+(z*240)), (new_display_buf+buf_inx));
buf_inx += 8;
}
}
This gives at least an order of magnitude improvement which is completely workable for my task; no more excessive lagginess! Though I am open to further optimizations that anyone would suggest. I'm sure my implementation of Mark's idea is far from optimized. Thanks again Mark!
What you need is a function that can transpose a block of 8x8 bits quickly, then you can run it on all 480 blocks in your display.
void transpose8x8bits(UBYTE * block, UBYTE * result)
{
int bit;
for (bit = 7; bit >= 0; bit--)
{
result[7-bit] = (((block[0] >> bit) & 1) << 7) |
(((block[1] >> bit) & 1) << 6) |
(((block[2] >> bit) & 1) << 5) |
(((block[3] >> bit) & 1) << 4) |
(((block[4] >> bit) & 1) << 3) |
(((block[5] >> bit) & 1) << 2) |
(((block[6] >> bit) & 1) << 1) |
((block[7] >> bit) & 1);
}
So I have a design which incorporates CRC32C checksums to ensure data hasn't been damaged. I decided to use CRC32C because I can have both a software version and a hardware-accelerated version if the computer the software runs on supports SSE 4.2
I'm going by Intel's developer manual (vol 2A), which seems to provide the algorithm behind the crc32 instruction. However, I'm having little luck. Intel's developer guide says the following:
BIT_REFLECT32: DEST[31-0] = SRC[0-31]
MOD2: Remainder from Polynomial division modulus 2
TEMP1[31-0] <- BIT_REFLECT(SRC[31-0])
TEMP2[31-0] <- BIT_REFLECT(DEST[31-0])
TEMP3[63-0] <- TEMP1[31-0] << 32
TEMP4[63-0] <- TEMP2[31-0] << 32
TEMP5[63-0] <- TEMP3[63-0] XOR TEMP4[63-0]
TEMP6[31-0] <- TEMP5[63-0] MOD2 0x11EDC6F41
DEST[31-0] <- BIT_REFLECT(TEMP6[31-0])
Now, as far as I can tell, I've done everything up to the line starting TEMP6 correctly, but I think I may be either misunderstanding the polynomial division, or implementing it incorrectly. If my understanding is correct, 1 / 1 mod 2 = 1, 0 / 1 mod 2 = 0, and both divides-by-zero are undefined.
What I don't understand is how binary division with 64-bit and 33-bit operands will work. If SRC is 0x00000000, and DEST is 0xFFFFFFFF, TEMP5[63-32] will be all set bits, while TEMP5[31-0] will be all unset bits.
If I was to use the bits from TEMP5 as the numerator, there would be 30 divisions by zero as the polynomial 11EDC6F41 is only 33 bits long (and so converting it to a 64-bit unsigned integer leaves the top 30 bits unset), and so the denominator is unset for 30 bits.
However, if I was to use the polynomial as the numerator, the bottom 32 bits of TEMP5 are unset, resulting in divides by zero there, and the top 30 bits of the result would be zero, as the top 30 bits of the numerator would be zero, as 0 / 1 mod 2 = 0.
Am I misunderstanding how this works? Just plain missing something? Or has Intel left out some crucial step in their documentation?
The reason I went to Intel's developer guide for what appeared to be the algorithm they used is because they used a 33-bit polynomial, and I wanted to make outputs identical, which didn't happen when I used the 32-bit polynomial 1EDC6F41 (show below).
uint32_t poly = 0x1EDC6F41, sres, crcTable[256], data = 0x00000000;
for (n = 0; n < 256; n++) {
sres = n;
for (k = 0; k < 8; k++)
sres = (sres & 1) == 1 ? poly ^ (sres >> 1) : (sres >> 1);
crcTable[n] = sres;
}
sres = 0xFFFFFFFF;
for (n = 0; n < 4; n++) {
sres = crcTable[(sres ^ data) & 0xFF] ^ (sres >> 8);
}
The above code produces 4138093821 as an output, and the crc32 opcode produces 2346497208 using the input 0x00000000.
Sorry if this is badly written or incomprehensible in places, it is rather late for me.
Here are both software and hardware versions of CRC-32C. The software version is optimized to process eight bytes at a time. The hardware version is optimized to run three crc32q instructions effectively in parallel on a single core, since the throughput of that instruction is one cycle, but the latency is three cycles.
crc32c.c:
/* crc32c.c -- compute CRC-32C using the Intel crc32 instruction
* Copyright (C) 2013, 2021 Mark Adler
* Version 1.2 5 Jun 2021 Mark Adler
*/
/*
This software is provided 'as-is', without any express or implied
warranty. In no event will the author be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. If you use this software
in a product, an acknowledgment in the product documentation would be
appreciated but is not required.
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
Mark Adler
madler#alumni.caltech.edu
*/
/* Version History:
1.0 10 Feb 2013 First version
1.1 31 May 2021 Correct register constraints on assembly instructions
Include pre-computed tables to avoid use of pthreads
Return zero for the CRC when buf is NULL, as initial value
1.2 5 Jun 2021 Make tables constant
*/
// Use hardware CRC instruction on Intel SSE 4.2 processors. This computes a
// CRC-32C, *not* the CRC-32 used by Ethernet and zip, gzip, etc. A software
// version is provided as a fall-back, as well as for speed comparisons.
#include <stddef.h>
#include <stdint.h>
// Tables for CRC word-wise calculation, definitions of LONG and SHORT, and CRC
// shifts by LONG and SHORT bytes.
#include "crc32c.h"
// Table-driven software version as a fall-back. This is about 15 times slower
// than using the hardware instructions. This assumes little-endian integers,
// as is the case on Intel processors that the assembler code here is for.
static uint32_t crc32c_sw(uint32_t crc, void const *buf, size_t len) {
if (buf == NULL)
return 0;
unsigned char const *data = buf;
while (len && ((uintptr_t)data & 7) != 0) {
crc = (crc >> 8) ^ crc32c_table[0][(crc ^ *data++) & 0xff];
len--;
}
size_t n = len >> 3;
for (size_t i = 0; i < n; i++) {
uint64_t word = crc ^ ((uint64_t const *)data)[i];
crc = crc32c_table[7][word & 0xff] ^
crc32c_table[6][(word >> 8) & 0xff] ^
crc32c_table[5][(word >> 16) & 0xff] ^
crc32c_table[4][(word >> 24) & 0xff] ^
crc32c_table[3][(word >> 32) & 0xff] ^
crc32c_table[2][(word >> 40) & 0xff] ^
crc32c_table[1][(word >> 48) & 0xff] ^
crc32c_table[0][word >> 56];
}
data += n << 3;
len &= 7;
while (len) {
len--;
crc = (crc >> 8) ^ crc32c_table[0][(crc ^ *data++) & 0xff];
}
return crc;
}
// Apply the zeros operator table to crc.
static uint32_t crc32c_shift(uint32_t const zeros[][256], uint32_t crc) {
return zeros[0][crc & 0xff] ^ zeros[1][(crc >> 8) & 0xff] ^
zeros[2][(crc >> 16) & 0xff] ^ zeros[3][crc >> 24];
}
// Compute CRC-32C using the Intel hardware instruction. Three crc32q
// instructions are run in parallel on a single core. This gives a
// factor-of-three speedup over a single crc32q instruction, since the
// throughput of that instruction is one cycle, but the latency is three
// cycles.
static uint32_t crc32c_hw(uint32_t crc, void const *buf, size_t len) {
if (buf == NULL)
return 0;
// Pre-process the crc.
uint64_t crc0 = crc ^ 0xffffffff;
// Compute the crc for up to seven leading bytes, bringing the data pointer
// to an eight-byte boundary.
unsigned char const *next = buf;
while (len && ((uintptr_t)next & 7) != 0) {
__asm__("crc32b\t" "(%1), %0"
: "+r"(crc0)
: "r"(next), "m"(*next));
next++;
len--;
}
// Compute the crc on sets of LONG*3 bytes, making use of three ALUs in
// parallel on a single core.
while (len >= LONG*3) {
uint64_t crc1 = 0;
uint64_t crc2 = 0;
unsigned char const *end = next + LONG;
do {
__asm__("crc32q\t" "(%3), %0\n\t"
"crc32q\t" LONGx1 "(%3), %1\n\t"
"crc32q\t" LONGx2 "(%3), %2"
: "+r"(crc0), "+r"(crc1), "+r"(crc2)
: "r"(next), "m"(*next));
next += 8;
} while (next < end);
crc0 = crc32c_shift(crc32c_long, crc0) ^ crc1;
crc0 = crc32c_shift(crc32c_long, crc0) ^ crc2;
next += LONG*2;
len -= LONG*3;
}
// Do the same thing, but now on SHORT*3 blocks for the remaining data less
// than a LONG*3 block.
while (len >= SHORT*3) {
uint64_t crc1 = 0;
uint64_t crc2 = 0;
unsigned char const *end = next + SHORT;
do {
__asm__("crc32q\t" "(%3), %0\n\t"
"crc32q\t" SHORTx1 "(%3), %1\n\t"
"crc32q\t" SHORTx2 "(%3), %2"
: "+r"(crc0), "+r"(crc1), "+r"(crc2)
: "r"(next), "m"(*next));
next += 8;
} while (next < end);
crc0 = crc32c_shift(crc32c_short, crc0) ^ crc1;
crc0 = crc32c_shift(crc32c_short, crc0) ^ crc2;
next += SHORT*2;
len -= SHORT*3;
}
// Compute the crc on the remaining eight-byte units less than a SHORT*3
// block.
unsigned char const *end = next + (len - (len & 7));
while (next < end) {
__asm__("crc32q\t" "(%1), %0"
: "+r"(crc0)
: "r"(next), "m"(*next));
next += 8;
}
len &= 7;
// Compute the crc for up to seven trailing bytes.
while (len) {
__asm__("crc32b\t" "(%1), %0"
: "+r"(crc0)
: "r"(next), "m"(*next));
next++;
len--;
}
// Return the crc, post-processed.
return ~(uint32_t)crc0;
}
// Check for SSE 4.2. SSE 4.2 was first supported in Nehalem processors
// introduced in November, 2008. This does not check for the existence of the
// cpuid instruction itself, which was introduced on the 486SL in 1992, so this
// will fail on earlier x86 processors. cpuid works on all Pentium and later
// processors.
#define SSE42(have) \
do { \
uint32_t eax, ecx; \
eax = 1; \
__asm__("cpuid" \
: "=c"(ecx) \
: "a"(eax) \
: "%ebx", "%edx"); \
(have) = (ecx >> 20) & 1; \
} while (0)
// Compute a CRC-32C. If the crc32 instruction is available, use the hardware
// version. Otherwise, use the software version.
uint32_t crc32c(uint32_t crc, void const *buf, size_t len) {
int sse42;
SSE42(sse42);
return sse42 ? crc32c_hw(crc, buf, len) : crc32c_sw(crc, buf, len);
}
Code to generate crc32c.h (stackoverflow won't let me post the tables themselves, due to a 30,000 character limit in an answer):
// Generate crc32c.h for crc32c.c.
#include <stdio.h>
#include <stdint.h>
#define LONG 8192
#define SHORT 256
// Print a 2-D table of four-byte constants in hex.
static void print_table(uint32_t *tab, size_t rows, size_t cols, char *name) {
printf("static uint32_t const %s[][%zu] = {\n", name, cols);
size_t end = rows * cols;
size_t k = 0;
for (;;) {
fputs(" {", stdout);
size_t n = 0, j = 0;
for (;;) {
printf("0x%08x", tab[k + n]);
if (++n == cols)
break;
putchar(',');
if (++j == 6) {
fputs("\n ", stdout);
j = 0;
}
putchar(' ');
}
k += cols;
if (k == end)
break;
puts("},");
}
puts("}\n};");
}
/* CRC-32C (iSCSI) polynomial in reversed bit order. */
#define POLY 0x82f63b78
static void crc32c_word_table(void) {
uint32_t table[8][256];
// Generate byte-wise table.
for (unsigned n = 0; n < 256; n++) {
uint32_t crc = ~n;
for (unsigned k = 0; k < 8; k++)
crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
table[0][n] = ~crc;
}
// Use byte-wise table to generate word-wise table.
for (unsigned n = 0; n < 256; n++) {
uint32_t crc = ~table[0][n];
for (unsigned k = 1; k < 8; k++) {
crc = table[0][crc & 0xff] ^ (crc >> 8);
table[k][n] = ~crc;
}
}
// Print table.
print_table(table[0], 8, 256, "crc32c_table");
}
// Return a(x) multiplied by b(x) modulo p(x), where p(x) is the CRC
// polynomial. For speed, this requires that a not be zero.
static uint32_t multmodp(uint32_t a, uint32_t b) {
uint32_t prod = 0;
for (;;) {
if (a & 0x80000000) {
prod ^= b;
if ((a & 0x7fffffff) == 0)
break;
}
a <<= 1;
b = b & 1 ? (b >> 1) ^ POLY : b >> 1;
}
return prod;
}
/* Take a length and build four lookup tables for applying the zeros operator
for that length, byte-by-byte, on the operand. */
static void crc32c_zero_table(size_t len, char *name) {
// Generate operator for len zeros.
uint32_t op = 0x80000000; // 1 (x^0)
uint32_t sq = op >> 4; // x^4
while (len) {
sq = multmodp(sq, sq); // x^2^(k+3), k == len bit position
if (len & 1)
op = multmodp(sq, op);
len >>= 1;
}
// Generate table to update each byte of a CRC using op.
uint32_t table[4][256];
for (unsigned n = 0; n < 256; n++) {
table[0][n] = multmodp(op, n);
table[1][n] = multmodp(op, n << 8);
table[2][n] = multmodp(op, n << 16);
table[3][n] = multmodp(op, n << 24);
}
// Print the table to stdout.
print_table(table[0], 4, 256, name);
}
int main(void) {
puts(
"// crc32c.h\n"
"// Tables and constants for crc32c.c software and hardware calculations.\n"
"\n"
"// Table for a 64-bits-at-a-time software CRC-32C calculation. This table\n"
"// has built into it the pre and post bit inversion of the CRC."
);
crc32c_word_table();
puts(
"\n// Block sizes for three-way parallel crc computation. LONG and SHORT\n"
"// must both be powers of two. The associated string constants must be set\n"
"// accordingly, for use in constructing the assembler instructions."
);
printf("#define LONG %d\n", LONG);
printf("#define LONGx1 \"%d\"\n", LONG);
printf("#define LONGx2 \"%d\"\n", 2 * LONG);
printf("#define SHORT %d\n", SHORT);
printf("#define SHORTx1 \"%d\"\n", SHORT);
printf("#define SHORTx2 \"%d\"\n", 2 * SHORT);
puts(
"\n// Table to shift a CRC-32C by LONG bytes."
);
crc32c_zero_table(8192, "crc32c_long");
puts(
"\n// Table to shift a CRC-32C by SHORT bytes."
);
crc32c_zero_table(256, "crc32c_short");
return 0;
}
Mark Adler's answer is correct and complete, but those seeking quick and easy way to integrate CRC-32C in their application might find it a little difficult to adapt the code, especially if they are using Windows and .NET.
I've created a library that implements CRC-32C using either hardware or software method depending on available hardware. It's available as a NuGet package for C++ and .NET. It's opensource of course.
Besides packaging Mark Adler's code above, I've found a simple way to improve throughput of the software fallback by 50%. On my computer, the library now achieves 2 GB/s in software and over 20 GB/s in hardware. For those curious, here's the optimized software implementation:
static uint32_t append_table(uint32_t crci, buffer input, size_t length)
{
buffer next = input;
#ifdef _M_X64
uint64_t crc;
#else
uint32_t crc;
#endif
crc = crci ^ 0xffffffff;
#ifdef _M_X64
while (length && ((uintptr_t)next & 7) != 0)
{
crc = table[0][(crc ^ *next++) & 0xff] ^ (crc >> 8);
--length;
}
while (length >= 16)
{
crc ^= *(uint64_t *)next;
uint64_t high = *(uint64_t *)(next + 8);
crc = table[15][crc & 0xff]
^ table[14][(crc >> 8) & 0xff]
^ table[13][(crc >> 16) & 0xff]
^ table[12][(crc >> 24) & 0xff]
^ table[11][(crc >> 32) & 0xff]
^ table[10][(crc >> 40) & 0xff]
^ table[9][(crc >> 48) & 0xff]
^ table[8][crc >> 56]
^ table[7][high & 0xff]
^ table[6][(high >> 8) & 0xff]
^ table[5][(high >> 16) & 0xff]
^ table[4][(high >> 24) & 0xff]
^ table[3][(high >> 32) & 0xff]
^ table[2][(high >> 40) & 0xff]
^ table[1][(high >> 48) & 0xff]
^ table[0][high >> 56];
next += 16;
length -= 16;
}
#else
while (length && ((uintptr_t)next & 3) != 0)
{
crc = table[0][(crc ^ *next++) & 0xff] ^ (crc >> 8);
--length;
}
while (length >= 12)
{
crc ^= *(uint32_t *)next;
uint32_t high = *(uint32_t *)(next + 4);
uint32_t high2 = *(uint32_t *)(next + 8);
crc = table[11][crc & 0xff]
^ table[10][(crc >> 8) & 0xff]
^ table[9][(crc >> 16) & 0xff]
^ table[8][crc >> 24]
^ table[7][high & 0xff]
^ table[6][(high >> 8) & 0xff]
^ table[5][(high >> 16) & 0xff]
^ table[4][high >> 24]
^ table[3][high2 & 0xff]
^ table[2][(high2 >> 8) & 0xff]
^ table[1][(high2 >> 16) & 0xff]
^ table[0][high2 >> 24];
next += 12;
length -= 12;
}
#endif
while (length)
{
crc = table[0][(crc ^ *next++) & 0xff] ^ (crc >> 8);
--length;
}
return (uint32_t)crc ^ 0xffffffff;
}
As you can see, it merely crunches larger block at a time. It needs larger lookup table, but it's still cache-friendly. The table is generated the same way, only with more rows.
One extra thing I explored is the use of PCLMULQDQ instruction to get hardware acceleration on AMD processors. I've managed to port Intel's CRC patch for zlib (also available on GitHub) to CRC-32C polynomial except the magic constant 0x9db42487. If anyone is able to decipher that one, please let me know. After supersaw7's excellent explanation on reddit, I have ported also the elusive 0x9db42487 constant and I just need to find some time to polish and test it.
First of all the Intel's CRC32 instruction serves to calculate CRC-32C (that is uses a different polynomial that regular CRC32. Look at the Wikipedia CRC32 entry)
To use Intel's hardware acceleration for CRC32C using gcc you can:
Inline assembly language in C code via the asm statement
Use intrinsics _mm_crc32_u8, _mm_crc32_u16, _mm_crc32_u32 or _mm_crc32_u64. See Intel Intrinsics Guide for a description of those for the Intel's compiler icc but gcc also implements them.
This is how you would do it with __mm_crc32_u8 that takes one byte at a time, using __mm_crc32_u64 would give further performance improvement since it takes 8 bytes at a time.
uint32_t sse42_crc32(const uint8_t *bytes, size_t len)
{
uint32_t hash = 0;
size_t i = 0;
for (i=0;i<len;i++) {
hash = _mm_crc32_u8(hash, bytes[i]);
}
return hash;
}
To compile this you need to pass -msse4.2 in CFLAGS. Like gcc -g -msse4.2 test.c otherwise it will complain about undefined reference to _mm_crc32_u8.
If you want to revert to a plain C implementation if the instruction is not available in the platform where the executable is running you can use GCC's ifunc attribute. Like
uint32_t sse42_crc32(const uint8_t *bytes, size_t len)
{
/* use _mm_crc32_u* here */
}
uint32_t default_crc32(const uint8_t *bytes, size_t len)
{
/* pure C implementation */
}
/* this will be called at load time to decide which function really use */
/* sse42_crc32 if SSE 4.2 is supported */
/* default_crc32 if not */
static void * resolve_crc32(void) {
__builtin_cpu_init();
if (__builtin_cpu_supports("sse4.2")) return sse42_crc32;
return default_crc32;
}
/* crc32() implementation will be resolved at load time to either */
/* sse42_crc32() or default_crc32() */
uint32_t crc32(const uint8_t *bytes, size_t len) __attribute__ ((ifunc ("resolve_crc32")));
I compare various algorithms here: https://github.com/htot/crc32c
The fastest algorithm has been taken from Intels crc_iscsi_v_pcl.asm assembly code (which is available in a modified form in the linux kernel) and using a C wrapper (crcintelasm.cc) included into this project.
To be able to run this code on 32 bit platforms first it has been ported to C (crc32intelc) where possible, a small amount of inline assembly is required. Certain parts of the code depend on the bitness, crc32q is not available on 32 bits and neither is movq, these are put in macro's (crc32intel.h) with alternative code for 32 bit platforms.
I have a device, which sends me Data with CRC Calculation.
Every 16 Bytes there are 2 CRC Bytes.
The generator polynomial is x16 + x13 + x12 + x11 + x10 + x8 + x6 + x5 + x2 + 1
My code looks like this:
int crc16(unsigned char *addr, int num, int crc)
{
uint16_t poly = 0x3D65;
int i;
for (; num > 0; num--) /* Step through bytes in memory */
{
crc = crc ^ ((unsigned short)*addr++ << 8); /* Fetch byte from memory, XOR into CRC top byte*/
for (i = 0; i < 8; i++) /* Prepare to rotate 8 bits */
{
if (crc & 0x10000) /* b15 is set... */
crc = (crc << 1) ^ poly; /* rotate and XOR with XMODEM polynomic */
else /* b15 is clear... */
crc <<= 1; /* just rotate */
} /* Loop for 8 bits */
crc &= 0xFFFF; /* Ensure CRC remains 16-bit value */
} /* Loop until num=0 */
return(crc); /* Return updated CRC */
}
I've also tried this code with other polynomials like 0x9CB2. I think there's an error located in the code.
Which compiler/platform are you using? Are you sure the int datatype is 32 bits? Try it with long and compare the results.
Also, there is a point in which you make the following if:
if ( crc & 0x10000 )
and in the comment you state that you are verifying the 15th bit. No, that's not true, you will be verifying the 16th bit. For the 15th it would be ( crc & 0x8000 ).