Steps to capture IRQs in arm64 GICv3? - arm

Question

I'm working on a bare-metal interrupt controller, GIC version 3. The underlying architecture is Virt, with QEMU, and a CPU Arm Cortex-72, aarch64:
qemu-system-aarch64 -machine virt,gic-version=3 -cpu cortex-a72 -nographic -kernel kernel.elf
According to the ARMv8-A guide, Interrupt Group 1 Enable register, bit 0 of register ICC_IGRPEN1_EL1 is the responsible for IRQs activation. This is an excerpt of it:
I specify that I work in NON SECURE mode.
I want to generate an IRQ from a timing context. The timer works well, but for any reason the IRQ is not captured even though bit 0of ICC_IGRPEN1_EL1 is set to 1.
Since I use several headers, I can't provide you a minimum example. I have no way, if you can suggest me how, please do it. However, I did the best possible to formulate a clear question, so I really hope you can help.
This is an excerpt of the function which shall generate the IRQ:
void timer_init(void)
{
uint64_t ticks, current_cnt;
// Disable the timer
disable_cntv();
//read system frequency
cntfrq = raw_read_cntfrq_el0();
// Next timer IRQ is after 3 sec(s).
ticks = 3 * cntfrq;
// Get value of the current timer
current_cnt = raw_read_cntvct_el0();
// Set the interrupt in Current Time + TimerTick
raw_write_cntv_cval_el0(current_cnt + ticks);
// Enable the timer
enable_cntv();
// Enable IRQ
enable_irqs();
while(1){
wfi();
}
}
Function enable_irqs has been defined as follows:
void enable_irqs(void) {
set_gic_gicc_igrpen1_el1(0x1);
}
In turn, function set_gic_gicc_igrpen1_el1 is:
void set_gic_gicc_igrpen1_el1(uint64_t value)
{
__asm__ __volatile__("msr s3_0_c12_c12_7 , %0" : : "r" (value));
}
I verified all the values with gdb: timer works and register ICC_IGRPEN1_EL1 has the last bit which is set to 1. Do you notice any errors in this code for which I do not receive any IRQs?
Not to be incomplete, the other functions I mentioned are implemented as follows:
void disable_cntv(void)
{
uint32_t cntv_ctl;
cntv_ctl = raw_read_cntv_ctl();
cntv_ctl &= ~CNTV_CTL_ENABLE;
__asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" : : "r" (cntv_ctl) : "memory");
}
void enable_cntv(void)
{
uint32_t cntv_ctl;
cntv_ctl = raw_read_cntv_ctl();
cntv_ctl |= CNTV_CTL_ENABLE;
__asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" : : "r" (cntv_ctl) : "memory");
}
uint32_t raw_read_cntfrq_el0(void)
{
uint32_t cntfrq_el0;
__asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
return cntfrq_el0;
}
void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0)
{
__asm__ __volatile__("msr CNTV_CVAL_EL0, %0\n\t" : : "r" (cntv_cval_el0) : "memory");
}
uint64_t raw_read_cntvct_el0(void)
{
uint64_t cntvct_el0;
__asm__ __volatile__("mrs %0, CNTVCT_EL0\n\t" : "=r" (cntvct_el0) : : "memory");
return cntvct_el0;
}
/* Wait For Interrupt */
#define wfi() asm volatile("wfi" : : : "memory")
CNTV_CTL_ENABLE is defined as follows:
#define CNTV_CTL_ENABLE (1 << 0) /* Enables the timer */