Generate library with makefile : No rule to make target - c

CC= gcc
CFLAGS= -Wall -g
INCLUDES= -I/usr/local/include/
LFLAGS= -L/usr/local/lib64
LDFLAGS=
LIBS= -L. -lrabbitmq
SRCS= amqp_connection.c amqp_consumer.c amqp_deconnection.c amqp_producer.c amqp_utils.c
OBJS= $(SRCS:.c=.o)
EXEC=amqp_test
.PHONY: all
all: $(EXEC)
#echo "$(MAKE) : Tout est généré"
$(EXEC): $(OBJS)
$(CC) $(CFLAGS) -o $(EXEC) $(OBJS) $(LDFLAGS) $(INCLUDES) $(LFLAGS) $(LIBS)
.PHONY: clean
clean:
$(RM) *~ *.o $(EXEC)
I want to generate a library not an executable
Can you help me please ?
I launched "make" and the result is :
make: *** No rule to make target
amqp_connection.o', needed by amqp_test'. Stop. amqp_test is the
name of the file which contain the main().
The sources are :
amqp_connection / amqp_consumer /amqp_deconnection / amqp_producer

This is an example file using some common practices. Here, I'm redefining the source directory and the object directory, and defining an implicit rule to build the objects given a source in a different directory.
CC := gcc
CFLAGS := -Wall -g
SRCDIR := src
OBJDIR := obj
INCLUDES := -I/usr/local/include/
LFLAGS := -L/usr/local/lib64
LDFLAGS :=
LIBS := -L. -lrabbitmq
SRCS_RAW := amqp_connection.c amqp_consumer.c amqp_deconnection.c amqp_producer.c amqp_utils.c
SRCS := $(addprefix $(SRCDIR)/,$(SRCS_RAW))
OBJS := $(addprefix $(OBJDIR)/,$(SRCS_RAW:.c=.o))
EXEC := amqp_test
$(info DEBUG: SRCS=$(SRCS))
$(info DEBUG: OBJS=$(OBJS))
$(info DEBUG: EXEC=$(EXEC))
.PHONY: all
all: $(EXEC)
#echo "$(MAKE) : Tout est généré"
$(EXEC): $(OBJS)
$(CC) $(CFLAGS) -o $(EXEC) $(OBJS) $(LDFLAGS) $(INCLUDES) $(LFLAGS) $(LIBS)
#rule to create object directory if it doesnt exist
$(OBJDIR):
mkdir $(OBJDIR)
#define implicit rule to build objects in their own directory
#(note -- order only dependency on object directory)
$(OBJS): $(OBJDIR)/%.o: $(SRCDIR)/%.c | $(OBJDIR)
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $#
.PHONY: clean
clean:
$(RM) *~ $(EXEC)
$(RM) -r $(OBJDIR)

Related

How to produce a generic Makefile for various projects with the same folder structure?

I have to following folder structure in various projects :
myproject/
obj/
src/
file1.c
file2.c
file3.c
inc/
myproject.h
Makefile
I have the following Makefile :
NAME := myproject
CC := gcc
RM := rm
CFLAGS := -Wall -Wextra -Werror
LDFLAGS := -Wall
RMFLAGS := -f
SRCDIR := src
OBJDIR := obj
INCDIR := inc
HEADERS := $(INCDIR)/myproject.h
LINK.o := $(CC) $(LDFLAGS)
COMPILE.c := $(CC) -I$(INCDIR) $(CFLAGS) -c
SRCS := file1.c file2.c file3.c
SOURCES := $(addprefix $(SRCDIR)/, $(SRCS))
OBJECTS := $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SOURCES))
$(OBJDIR)/%.o: $(SRCDIR)/%.c
$(COMPILE.c) $< -o $#
all: $(NAME)
$(NAME): $(OBJECTS) $(HEADERS) Makefile
$(LINK.o) $< -o $#
clean:
$(RM) $(OBJECTS)
fclean: clean
$(RM) $(NAME)
re: fclean all
.PHONY: all clean fclean re
Here is what I am looking to achieve :
I would like to put all .o files under obj/.
The final executable should be at the root of the myproject/ folder.
If a .c file changes, only this file should be recompiled.
If the Makefile or the .h changes, I would like to recompile everything.
However, I when I run this Makefile I get make: *** No rule to make target obj/file1.o', needed by myproject'. Stop..
Could anyone help me fix this Makefile and give me advice on how to improve it?
EDIT
Here is a new version of the Makefile based on the comments.
NAME := myproject
CC := gcc
RM := rm
CFLAGS := -Wall -Wextra -Werror
LDFLAGS := -Wall
RMFLAGS := -f
SRCDIR := src
OBJDIR := obj
INCDIR := inc
HEADERS := $(INCDIR)/myproject.h
LINK.o := $(CC) $(LDFLAGS)
COMPILE.c := $(CC) -I$(INCDIR) $(CFLAGS) -c
REMOVE := $(RM) $(RMFLAGS)
SRCS := file1.c file2.c file3.c
SOURCES := $(addprefix $(SRCDIR)/, $(SRCS))
OBJECTS := $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SOURCES))
$(OBJDIR)/%.o: $(SRCDIR)/%.c
$(COMPILE.c) $< -o $#
all: $(NAME)
$(NAME): $(OBJECTS)
$(LINK.o) -o $(NAME) $^
clean:
$(REMOVE) $(OBJECTS)
fclean: clean
$(REMOVE) $(NAME)
re: fclean all
.PHONY: all clean fclean re
This version works, but I am still unsure how to trigger recompilation of the Makefile or the .h changes.
Thanks to #MadScientist and #HardcoreHenry I have managed to fix the Makefile. Here is the final version :
# Edit the $(NAME) and $(SRCS) variables as necessary.
NAME := myprogram
SRCS := file1.c file2.c file3.c
CC := gcc
RM := rm
CFLAGS := -Wall -Wextra -Werror
LDFLAGS := -Wall
RMFLAGS := -f
SRCDIR := src
OBJDIR := obj
INCDIR := inc
# Edit the $(HEADERS) variable as necessary.
HEADERS := $(INCDIR)/myprogram.h
LINK.o := $(CC) $(LDFLAGS)
COMPILE.c := $(CC) -I$(INCDIR) $(CFLAGS) -c
REMOVE := $(RM) $(RMFLAGS)
SOURCES := $(addprefix $(SRCDIR)/, $(SRCS))
OBJECTS := $(patsubst $(SRCDIR)/%.c, $(OBJDIR)/%.o, $(SOURCES))
$(OBJDIR)/%.o: $(SRCDIR)/%.c
#mkdir -p $(#D)
$(COMPILE.c) $< -o $#
all: $(NAME)
$(OBJECTS): $(HEADERS) Makefile
$(NAME): $(OBJECTS)
$(LINK.o) -o $(NAME) $^
clean:
$(REMOVE) $(OBJECTS)
fclean: clean
$(REMOVE) $(NAME)
re: fclean all
.PHONY: all clean fclean re

Generate executable file with makefile in linux

I want to generate two executable file from two sources.
What should i put in the Flag EXEC ?
Is this line correct? --> EXEC := amqp_consommateur amqp_producteur
CC := gcc
CFLAGS := -Wall -g
SRCDIR := src
OBJDIR := obj
INCLUDES := -I/usr/local/include/ -I/home/tvi/projets/RabbitMQ/libamqp/dlo -I/home/tvi/projets/RabbitMQ/rabbitmq-c/librabbitmq
LFLAGS := -L/usr/local/lib64
LDFLAGS :=
LIBS := -L. -lrabbitmq
SRCS_RAW := amqp_consommateur.c amqp_producteur.c
SRCS := $(addprefix $(SRCDIR)/,$(SRCS_RAW))
OBJS := $(addprefix $(OBJDIR)/,$(SRCS_RAW:.c=.o))
EXEC := amqp_consommateur amqp_producteur
$(info DEBUG: SRCS=$(SRCS))
$(info DEBUG: OBJS=$(OBJS))
$(info DEBUG: EXEC=$(EXEC))
.PHONY: all
all: $(EXEC)
#echo "$(MAKE) : Tout est généré"
$(EXEC): $(OBJS)
$(CC) $(CFLAGS) -o $(EXEC) $(OBJS) $(LDFLAGS) $(INCLUDES) $(LFLAGS) $(LIBS)
#rule to create object directory if it doesnt exist
$(OBJDIR):
mkdir $(OBJDIR)
#define implicit rule to build objects in their own directory
#(note -- order only dependency on object directory)
$(OBJS): $(OBJDIR)/%.o: $(SRCDIR)/%.c | $(OBJDIR)
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $#
.PHONY: clean
clean:
$(RM) *~ $(EXEC)
$(RM) -r $(OBJDIR)

Makefile is not creating a directory

Teacher gave us this makefile for compiling two C files and storing the objects into a directory called object. It compiles the programs fine however it doesn't store their objects into the directory, and it also doesn't even create the directory. Not sure what to do and could really use some help.
This is my make file
CC = clang
CFLAGS = -g -Wall
OBJDIR = object
HDRS = $(wildcard *.h)
SRCS = $(wildcard *.c)
OBJS = $(addprefix $(OBJDIR)/, $(SRCS:.c=.o))
.PHONY: all
all: client server
# WARNING: must have a tab before each definition
$(OBJDIR)/client.o: client.c $(HDRS) $(OBJDIR)
$(CC) $(CFLAGS) -c client.c -o object/client.o
$(OBJDIR)/server .o: server.c $(HDRS) $(OBJDIR)
$(CC) $(CFLAGS) -c server.c -o object/server.o
$(OBJDIR)/%.o: %.c $(HDRS) $(OBJDIR)
$(CC) $(CFLAGS) -c $*.c -o object/$*.o
$(OBJDIR):
mkdir $(OBJDIR)
.PHONY: clean
clean:
rm -f $(TARGET) $(OBJS)
All I had to do was add multiple targets to the makefile and change all to target the targets
CC = clang
CFLAGS = -g -Wall
# TODO: rename the target to something meaningful!
TARGET = client server
OBJDIR = object
HDRS = $(wildcard *.h)
SRCS = $(wildcard *.c)
OBJS = $(addprefix $(OBJDIR)/, $(SRCS:.c=.o))
.PHONY: all
all: $(TARGET)
# WARNING: *must* have a tab before each definition
$(TARGET): $(OBJDIR) $(OBJS)
$(CC) $(CFLAGS) $(OBJDIR)/protocol.o $(OBJDIR)/$#.o -o $#
$(OBJDIR)/%.o: %.c $(HDRS) $(OBJDIR)
$(CC) $(CFLAGS) -c $*.c -o object/$*.o
$(OBJDIR):
mkdir $(OBJDIR)
.PHONY: clean
clean:
rm -f $(TARGET) $(OBJS)

How to explicitly link library path via makefile

I installed a real-time library libre from brew install libre in my macOS. It is located in the directory /usr/local/Cellar/libre/0.5.7. I am trying to explicitly add this path in Makefile so I declare RT_LIBS_PATH=-L/usr/local/Cellar/libre/0.5.7. The entire makefile looks like this:
TARGET = run
LIBS = -O2 -lm
CC = gcc-7
CFLAGS = -fopenmp
RT_LIBS_PATH=-L/usr/local/Cellar/libre/0.5.7/lib
.PHONY: default all clean
all: $(TARGET)
OBJECTS = $(patsubst %.c, %.o, $(wildcard *.c))
HEADERS = $(wildcard *.h)
%.o: %.c $(HEADERS)
#$(CC) $(CFLAGS) $(RT_LIBS_PATH) -c $< -o $#
.PRECIOUS: $(TARGET) $(OBJECTS)
$(TARGET): $(OBJECTS)
#$(CC) $(OBJECTS) $(CFLAGS) $(LIBS) -o $#
clean:
-rm -f *.o
-rm -f $(TARGET)
However, it seems makefile does not recognize the libre, thus I assume I use RT_LIBS_PATH=-L/usr/local/Cellar/libre/0.5.7/lib in a wrong way. Kindly, is there something wrong in this way?
You have to specified library path when you are creating .o, you have to specify it when link all objs into executable
$(TARGET): $(OBJECTS)
#$(CC) $(OBJECTS) $(CFLAGS) $(RT_LIBS_PATH) $(LIBS) -o $#

Makefile - compiling library and executable when no changes made

So, I can understand what the problem is here, but I can't quite figure out how to fix it -- Because it is compiling files from a different directory, but throwing the .a library file and executable into the root...It seems that the makefile is expecting them to be in their source directory, and that's why it rebuilds every time even when no changes are made.
Problem is, my school is very strict on folder structure, so it needs to compile exactly how it is, I just need to figure out how to let the makefile know the executable and library file DO exist, in the root directory.
Here is my Makefile:
NAME = fillit
LIB = libft.a
CC = gcc
CFLAGS = -Wall -Wextra -Werror
RM = /bin/rm -rf
SRC = main.c validation.c create_piece.c game_board.c solver.c tables.c \
trimmer.c
LIBSRC = ft_putchar.c ft_putstr.c ft_strcpy.c ft_strnew.c ft_strdel.c \
ft_strequ.c ft_putendl.c ft_error.c
LIBLIST := $(shell ls -1 libft | grep .c$$)
LIBOBJ := $(LIBLIST:.c=.o)
LIBOBJ := $(addprefix libft/, $(LIBOBJ))
SRCLIST := $(shell ls -1 src | grep .c$$)
SRCOBJ := $(SRCLIST:.c=.o)
SRCOBJ := $(addprefix src/, $(SRCOBJ))
.PHONY: all $(NAME) lib
all: $(NAME)
libft/%.o: libft/%.c
$(CC) $(CFLAGS) -c -o $# $<
src/%.o: src/%.c
$(CC) $(CFLAGS) -c -o $# $<
lib:
ar rc $(LIB) $(LIBOBJ)
ranlib $(LIB)
debug:
$(CC) $(CFLAGS) $(addprefix libft/, $(LIBLIST)) $(addprefix src/, $(SRCLIST)) -g -o fillit
$(NAME): $(LIBOBJ) $(SRCOBJ) lib
$(CC) $(CFLAGS) $(SRCOBJ) -L. -lft -o fillit
clean:
$(RM) $(SRCOBJ)
$(RM) $(LIBOBJ)
fclean: clean
$(RM) $(NAME)
$(RM) $(LIB)
re: fclean all
re-db: fclean debug
It's working fine for compiling the .o files, it only does that once, but if I continue to type make, it still compiles this part:
➜ fillit git:(master) ✗ make
ar rc libft.a libft/ft_memset.o libft/ft_putchar.o libft/ft_putendl.o libft/ft_putstr.o libft/ft_strcpy.o libft/ft_strdel.o libft/ft_strequ.o libft/ft_strnew.o
ranlib libft.a
gcc -Wall -Wextra -Werror src/create_piece.o src/game_board.o src/main.o src/solver.o src/tables.o src/trimmer.o src/validation.o -L. -lft -o fillit
Want to thank kaylum for pointing me in the right direction, I have figured out how to solve this problem. I changed lib to $(LIB) and removed $(NAME) and lib from the phony list. Working makefile:
NAME = fillit
LIB = libft.a
CC = gcc
CFLAGS = -Wall -Wextra -Werror
RM = /bin/rm -rf
SRC = main.c validation.c create_piece.c game_board.c solver.c tables.c \
trimmer.c
LIBSRC = ft_putchar.c ft_putstr.c ft_strcpy.c ft_strnew.c ft_strdel.c \
ft_strequ.c ft_putendl.c ft_error.c
LIBLIST := $(shell ls -1 libft | grep .c$$)
LIBOBJ := $(LIBLIST:.c=.o)
LIBOBJ := $(addprefix libft/, $(LIBOBJ))
SRCLIST := $(shell ls -1 src | grep .c$$)
SRCOBJ := $(SRCLIST:.c=.o)
SRCOBJ := $(addprefix src/, $(SRCOBJ))
.PHONY: all
all: $(NAME)
libft/%.o: libft/%.c
$(CC) $(CFLAGS) -c -o $# $<
src/%.o: src/%.c
$(CC) $(CFLAGS) -c -o $# $<
$(LIB):
ar rc $(LIB) $(LIBOBJ)
ranlib $(LIB)
debug:
$(CC) $(CFLAGS) $(addprefix libft/, $(LIBLIST)) $(addprefix src/, $(SRCLIST)) -g -o fillit
$(NAME): $(LIBOBJ) $(SRCOBJ) $(LIB)
$(CC) $(CFLAGS) $(SRCOBJ) -L. -lft -o $(NAME)
clean:
$(RM) $(SRCOBJ)
$(RM) $(LIBOBJ)
fclean: clean
$(RM) $(NAME)
$(RM) $(LIB)
re: fclean all
re-db: fclean debug

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