About generating makefile prerequisites automatically - c

Question

I'm working on Stanford CS107 assignment 3, in which we implement a C version "vector". In the end I have some files in my directory,
.
├── Makefile
├── bool.h
├── vector.c
├── vector.h
└── vectortest.c
My question is about the handout Makefile, which looks like that,
CC = gcc
CFLAGS = -g -Wall -std=gnu11 -Wpointer-arith
LDFLAGS =
VECTOR_SRCS = vector.c
VECTOR_HDRS = $(VECTOR_SRCS:.c=.h)
VECTOR_TEST_SRCS = vectortest.c $(VECTOR_SRCS)
VECTOR_TEST_OBJS = $(VECTOR_TEST_SRCS:.c=.o)
SRCS = $(VECTOR_SRCS) vectortest.c
HDRS = $(VECTOR_HDRS)
EXECUTABLES = vector-test
default: $(EXECUTABLES)
vector-test: Makefile.dependencies $(VECTOR_TEST_OBJS)
$(CC) $(CFLAGS) -o $# $(VECTOR_TEST_OBJS) $(LDFLAGS)
# The dependencies below make use of make's default rules,
# under which a .o automatically depends on its .c and
# the action taken uses the $(CC) and $(CFLAGS) variables.
# These lines describe a few extra dependencies involved.
Makefile.dependencies:: $(SRCS) $(HDRS)
$(CC) $(CFLAGS) -MM $(SRCS) > Makefile.dependencies
-include Makefile.dependencies
.PHONY: clean
clean:
-rm -fr $(EXECUTABLES) *.o core Makefile.dependencies
When I run make vector-test, a file Makefile.dependencies was generated, in which lies some "default rules" of make,
vector.o: vector.c vector.h bool.h
vectortest.o: vectortest.c vector.h bool.h
My question is: professor keep the result of preprocess in another file is just to show us what the "default rules" is, or it's for some efficiency reason? For example GNU-GCC-3.22 Using Precompiled Headers can save times by preventing compile from processing header files over and over again? Because normally we don't have to list all .h files, and simply do gcc -c vector.c, or leave everything to the implicit rules. Am I right?
Another question is why he use :: instead of : here? I didn't find some useful information online talking about that. Thanks guys!

Answer 1

professor keep the result of preprocess in another file
Not true. According to your makefile, preprocessing result is not stored in any files. Preprocessing is a result of running preprocessor on your source files, i.e. it will substitute the contents of header files in place of #include directives and evaluate and substitute macros.
Instead, in your makefile, a header dependency rules are generated and stored in Makefile.dependencies. The -MM key of gcc generates header dependency rules, so that in case you edit one of the header files on which your source files depend, those source files will be recompiled next time you invoke make.
In your makefile you then include the generated dependency rules with -include Makefile.dependencies, so that make picks up header dependency rules generated by previous make invocation.
The contents of Makefile.dependencies, as you have noticed, are a valid makefile syntax.
See https://www.gnu.org/software/make/manual/html_node/Automatic-Prerequisites.html for more info.
So, this is kind of efficiency reasons, so that you can avoid rebuilding all, by cleaning first in case some of the header files are edited. But also, it is a convenience reason, that you don't have to worry about remembering to clean and rebuild all in case you have edited some of the header files. The make utility will rebuild only affected source files.
Precomiled headers is not related to that.

Answer 2

Thanks #igagis and #MadScientist for following great references:
Mad-Scientist.net - Auto-Dependency Generation
GNU - Generating Prerequisites Automatically
GNU - How Makefiles Are Remade
The follow content is just a simple conclusion of Mad-Scientist.net - Auto-Dependency Generation, for more information please check the original link.
In short, there are two conventional practices to generate prerequisites automatically,
Old-school way is to use gcc -MM to create a single dependencies file.
vector.o: vector.c vector.h bool.h
vectortest.o: vectortest.c vector.h bool.h
The code snippet looks like,
depend:: $(SRCS) $(HDRS)
$(CC) $(CFLAGS) -MM $(SRCS) $(LDFLAGS) > $(DEP_FILE)
-include $(DEP_FILE)
This practice has two main problems:
You have to explicitly run make depend to keep dependencies file up to date.
It is inefficient to rebuild all dependencies if any tiny change is made in source code, especially when you have a large scale project to manage.
A second modern way solves above problems by separating each dependency rule into one .d file.
In vector.d:
vector.o vector.d: vector.c vector.h bool.h
In vectortest.d
vectortest.o vectortest.d: vectortest.c vector.h bool.h
The point here is that when make read the above rule in .d file, before it does anything, it will try to rebuild included .d file automatically, and that makes the difference. People don't have to explicitly run make depend.
The following snippet is not the final version but to give you a little taste about what the code looks like. There are some little tricks hiding behind, check the references above for complete solution.
%.d: %.c
#set -e; rm -f $#; \
$(CC) -M $(CPPFLAGS) $< > $#.$$$$; \
sed 's,\($*\)\.o[ :]*,\1.o $# : ,g' < $#.$$$$ > $#; \
rm -f $#.$$$$
-include $(wildcard $(SRCS:.c=.d))
Currently I feel comfortable with the first practice, because it's quite simple and good enough for most of my personal use case. And here is the complete Makefile for this assignment.
# 1. C11 is the newest version of C language
# 2. -Wpointer-arith request a warning when addtion and subtraction are done
# on pointers to void and to functions, which is supported in GNU C.
CC = gcc
CFLAGS = -g -Wall -std=gnu11 -Wpointer-arith
LDFLAGS =
VECTOR_SRCS = vector.c
VECTOR_HDRS = $(VECTOR_SRCS:.c=.h)
VECTOR_OBJS = $(VECTOR_SRCS:.c=.o)
VECTOR_TEST_SRCS = vectortest.c $(VECTOR_SRCS)
VECTOR_TEST_OBJS = $(VECTOR_TEST_SRCS:.c=.o)
SRCS = $(VECTOR_SRCS) vectortest.c
HDRS = $(VECTOR_HDRS)
OBJS = $(SRCS:.c=.o)
EXES = vectortest
DEP_DIR = ./deps
DEP_FILE = $(DEP_DIR)/Makefile.dependencies
.PHONY: default depend clean
default: $(EXES)
# 1. The dependencies below make use of make's default rules,
# under which a .o automatically depends on its .c and
# the action taken uses the $(CC) and $(CFLAGS) variables.
# These lines describe a few extra dependencies involved.
#
# 2. -MMD means write a dependencies file containing user headers.
# -MM likes -MMD, but also implies -E only do preprocess,
# and write to stand out by default.
depend:: $(SRCS) $(HDRS)
$(CC) $(CFLAGS) -MM $(SRCS) $(LDFLAGS) > $(DEP_FILE)
-include $(DEP_FILE)
vectortest: $(VECTOR_TEST_OBJS) depend
$(CC) $(CFLAGS) -o $# $(VECTOR_TEST_OBJS) $(LDFLAGS)
clean:
-rm -f *.o $(EXES) $(DEP_FILE)