I am trying to convert my ez80 program to .8xp for my ti 83 premium ce with fasmg and the ez80-lib but i got the following error when trying to compile :
INCLUDE="include;include/fasmg-ez80" fasmg DragonLairTI.asm DragonLairTI.8xp
/bin/sh: /c/Program Files (x86)/fasmg/fasmg: cannot execute binary file: Exec format error
make: *** [Makefile:28: DragonLairTI.8xp] Error 126
The makefile is simple :
INCLUDES = $(addprefix include/,$(addprefix fasmg-ez80/,ez80.inc commands.alm ez80.alm) ti84pceg.inc)
all: DragonLairTI
unprot: FASMG_FLAGS = -i "protected equ"
unprot: all
$(MV) DragonLairTI.8xp
$(MAKE)
$(ZIP) DragonLairTI.zip DragonLairTI.8xp
%.8xp: %.asm $(INCLUDES) Makefile
INCLUDE="include;include/fasmg-ez80" $(FASMG) $(FASMG_FLAGS) $< $#
include/ti84pceg.inc: include/ti84pce.inc Makefile
include/fasmg-ez80/ti84pce.sed $< > $#
$(SED) --expression='3s/^/element anovaf_vars\n/' --in-place $#
include/ti84pce.inc: include/fasmg-ez80/bin/fetch_ti84pce Makefile
$(MKDIR) include
$(CD) include && fasmg-ez80/bin/fetch_ti84pce
Any idea how can i fix it ?
If you want to recreate the bug , i tried , you can use the app of the creator of the ez80 lib : https://github.com/jacobly0/asmhook
Related
Automate the compilation of auto-generated C files with regular C files
We have developed a program "cperformer" that is able to generate a C file from a text file (to keep it simple).
It is a kind of "meta-compiler" that generates C file as output. Thus, we would like to improve the usage of this "C generator" by automating the generation of each C file as a first step of a makefile, and then compile and link together all of these generated C files with other C files already present with GCC in the same makefile.
Makefile 1
C_GEN :=./cperformer -n
CC :=gcc
CFLAGS :=-I.
#List all .c files generated from .text files
AUTO_SRCS = $(wildcard *.text)
AUTO_OBJS_C := $(patsubst %.text,%_alg.c,$(AUTO_SRCS))
$(info *INFO* Text files = $(AUTO_SRCS))
#List all .c files to compile (auto-generated or not)
SRCS = $(AUTO_OBJS_C)
SRCS += $(wildcard *.c)
OBJS := $(patsubst %.c,%.o,$(SRCS))
$(info *INFO* C files = $(SRCS))
# Main target rule
target : $(OBJS)
$(CC) -o $# $(OBJS) $(CFLAGS)
# Pre-compilation step (some C files generation)
prelim $(AUTO_OBJS_C): $(AUTO_SRCS)
$(C_GEN) $<
# Pre-compilation step (object files generation)
%.o: %.c
$(CC) -c -o $# $< $(CFLAGS)
all: prelim target
clean :
rm -f TARGET $(OBJS) *_alg*
Error 1
$ make all
*INFO* Text files = file3.text file2.text file1.text
*INFO* C files = file3_alg.c file2_alg.c file1_alg.c linked_list.c main.c
./cperformer -n file3.text
Compiling: file3.text ...
No error.
Done.
gcc -c -o file3_alg.o file3_alg.c -I.
./cperformer -n file3.text
Compiling: file3.text ...
No error.
Done.
gcc -c -o file2_alg.o file2_alg.c -I.
gcc: error: file2_alg.c: No such file or directory
gcc: fatal error: no input files
compilation terminated.
make: *** [Makefile:29: file2_alg.o] Error 1
It fails because the "cperformer" program is asked to generate the same C file each time "file3.c" so GCC don't find "file2.c" as expected and it aborts the compilation.
Makefile 2
Replace the C generative rule of the above makefile with the use of "%" :
# Pre-compilation step (some C files generation)
%.c: %.text
$(C_GEN) $<
Error 2
make: *** No rule to make target 'file3_alg.o', needed by 'target'. Stop.
Nothing compiles here.
Makefile 3
The dirty fix
batch_c_generation :
#$(foreach TXT_FILE, $(AUTO_SRCS), $(C_GEN) $(TXT_FILE);)
This is kind of working but remains very dirty because it re-generates all C files at each build and some duplication errors appear when it is not properly cleared between each make.
How can I fix the makefile ?
You were close -- simply fix your pattern rule to look like this:
%_alg.c : %.text
$(C_GEN) $<
As #tripleee mentioned, the reason your makefile1 rule failed was that it expands to something like:
file2_alg.c file1_alg.c: file2.text file1.text
$(CGEN) $<
In this case $< expands to the first dependency which will always be file2.text...
In your makefile2 example, you used %.c instead of %_alg.c (and hence there's no rule to build file2_alg.c, and therefore no rule to build file2_alg.o)
CC := cc
NAME := minishell
SRCS = ./Srcs/xsh.c
DIR = .build
OBJS := $(SRCS:%.c=$(DIR)%.o)
OBJS := $(addprefix $(DIR), $(OBJS))
$(DIR)/%.o : %.c
$(CC) -c -o $# $<
$(NAME) : $(OBJS) | $(DIR)
$(CC) -o $# $^
$(DIR):
mkdir -p $(#)
all : $(NAME)
I am trying to store all .o files in the build directory
Makefile:12: warning: overriding commands for target .build
Makefile:8: warning: ignoring old commands for target .build
make: *** No rule to make target %.c, needed by .build. Stop
Your line numbers are off by one which makes these errors hard to understand. Please be sure to include the exact makefile and errors so that they match up.
However, I assume that line #8 is:
$(DIR)/%.o : %.c
and line #12 is:
$(DIR):
The only way that this could give that error is if your DIR variable ended in spaces:
DIR = .build
^-space here
Makefiles preserve ending spaces on variables so be sure you don't do that.
Note if you had a newer version of GNU make it would warn about this:
Makefile:8: *** mixed implicit and normal rules: deprecated syntax
I guess that's still not super-helpful but it's something! :)
I'm new to Stack Overflow. I'm currently having a hard time solving a simple problem.
In my shell/ directory, I have:
CVS/
include/
Makefile
obj
src
My problem occurs when trying to direct object files to be built in obj, but when I run make with the following code:
# Beginning of Makefile
OBJS = obj/shutil.o obj/parser.o obj/sshell.o
HEADER_FILES = include/shell.h include/parser.h
EXECUTABLE = simpleshell
CFLAGS = -Wall
CC = gcc
# End of configuration options
#What needs to be built to make all files and dependencies
all: $(EXECUTABLE)
#Create the main executable
$(EXECUTABLE): $(OBJS)
$(CC) -o $(EXECUTABLE) $(OBJS)
#Recursively build object files
%.o: %.c
$(CC) $(CFLAGS) -c -o $# $<
#Define dependencies for objects based on header files
#We are overly conservative here, parser.o should depend on parser.h only
$(OBJS) : $(HEADER_FILES)
clean:
-rm -f $(EXECUTABLE) obj/*.o
run: $(EXECUTABLE)
./$(EXECUTABLE)
tarball:
-rm -f $(EXECUTABLE) obj/*.o
(cd .. ; tar czf Kevin_Fairchild_a3.tar.z shell )
# End of Makefile
I get this error:
gcc -o simpleshell obj/shutil.o obj/parser.o obj/sshell.o
gcc: obj/shutil.o: No such file or directory
gcc: obj/parser.o: No such file or directory
gcc: obj/sshell.o: No such file or directory
gcc: no input files
make: *** [simpleshell] Error 1
What simple piece am I missing? I will continue to research and learn more about Makefiles
The trouble is that the pattern rule
%.o: %.c
...
doesn't actually match what you're trying to do. The source file is actually src/shutil.c, so this rule doesn't fit. All Make sees is this rule:
$(OBJS) : $(HEADER_FILES)
There are no commands, so Make concludes that no action is necessary. It then proceeds with the rule for simpleshell, which fails because the objects aren't there.
Try this:
obj/%.o: src/%.c
$(CC) $(CFLAGS) -c -o $# $<
There are more sophisticated variations, once this much is working.
after adding that simple modification, which I originally attempted before posting here, i.e.
obj/%.o: src/%.c
I recieved this error, so originally I though it was something else.
gcc -Wall -c -o obj/shutil.o
src/shutil.c
src/shutil.c:14:19: error: shell.h: No such file or directory
src/shutil.c: In function ‘signal_c_init’:
src/shutil.c:72: error: ‘waitchildren’ undeclared (first use in this function)
src/shutil.c:72: error: (Each undeclared identifier is reported only once
src/shutil.c:72: error: for each function it appears in.)
src/shutil.c: In function ‘checkbackground’:
src/shutil.c:90: warning: implicit declaration of function ‘striptrailingchar’
src/shutil.c: At top level:
src/shutil.c:101: warning: conflicting types for ‘striptrailingchar’
src/shutil.c:90: note: previous implicit declaration of ‘striptrailingchar’ was here
make: *** [obj/shutil.o] Error 1`
Thanks for the quick reply by the way!
I have a root directory and a child directory. I am planning to put the functions in child directory under libfunc.o
This libfunc.o should be merged along with other object files in top directory. But I am getting error:
$make all
cd folder; make libfunc.o
make[1]: Entering directory `/home/Work/test_makefile/folder'
cc -c -o func2.o func2.c
cc -c -o func3.o func3.c
func3.c: In function ‘set’:
func3.c:3:25: warning: initialization makes pointer from integer without a cast [enabled by default]
ld -r -o libfunc.o func2.o func3.o
make[1]: Leaving directory `/home/Work/test_makefile/folder'
arm-linux-gnueabi-gcc -c -o hellofun.o hellofun.c -I. -I./include
arm-linux-gnueabi-gcc -c -o hellomake.o hellomake.c -I. -I./include
arm-linux-gnueabi-gcc hellofun.o hellomake.o folder/libfunc.o -o hm
folder/libfunc.o: file not recognized: File format not recognized
collect2: ld returned 1 exit status
make: *** [hm] Error 1
Makefiles: toplevel
1 CC=arm-linux-gnueabi-gcc
2 LD=arm-linux-gnueabi-ld
3 AR=arm-linux-gnueabi-ar
4 CFLAGS=-I. -I./include
5 SOURCES=hellofun.c hellomake.c
6 OBJECTS=$(SOURCES:.c=.o)
7 SUBDIR_OBJS=folder/libfunc.o
8 TARGET=hm
9 DEPS = hellomake.h
10
11 %.o: %.c $(DEPS) $(SUBDIR_OBJS)
12 $(CC) -c -o $# $< $(CFLAGS)
13
14 folder/libfunc.o:
15 cd folder; $(MAKE) libfunc.o
16
17 clean:
18 rm -rf *.o hellomake folder/*.o
19
20 all: $(SOURCES) $(TARGET)
21
22 $(TARGET): $(OBJECTS)
23 $(CC) $(OBJECTS) $(SUBDIR_OBJS) -o $#
24
Makefile : Child
1 SOURCES=$(wildcard *.c)
2 OBJECTS=$(SOURCES:.c=.o)
3 TARGET=libfunc.o
4 %.o: %.c
5 $(CC) -c -o $# $< $(CFLAGS)
6
7 clean:
8 rm -rf *.o
9
10
11 $(TARGET): $(OBJECTS)
12 $(if $(strip $(OBJECTS)),\
13 $(LD) $(LDFLAGS) -r -o $# $(OBJECTS),\
14 rm -f $#; $(AR) rcs $# )
~
~
~
There's more than one error here. First, when asking questions please always provide the complete error message. The no rule to make target error will print out which target it's trying to make; that's critical information for helping you.
Second, you reference a variable SUBDIR_OBJS, but that's never defined. Plus you list that as a prerequisite for building other object files in the %.o : %.c rule: it's virtually never correct to list object files as prerequisites of other object files.
The top-level makefile does not run make in the folder directory, so no commands in that directory will be run automatically. You'll have to go there and run make yourself by hand.
Also in config.mk you create a variable merge_object but in folder/Makefile you refer to a variable merge_objects, which is not the same variable.
I missed export CC in root makefile
I would suggest put on the -Wall option in your compiler options, so that you can have a better debug view of your compiling process.
The output ld -r -o libfunc.o func2.o func3.o seems suspicious to me. Looks like The system used default linker rather than your cross-compile linker, which is arm-linux-gnueabi-ld. That might be a reason for the file not recognized.
As the error was file format not recognized, maybe you can check file libfunc.o output?
If you are having with LD, why not skip it and try other methods, like just gcc -o hm with all object files, or use ar to package the objects in subfolder.
I am in the process of porting some code that was developed in the codeblocks IDE. I am transferring it to a Linux server where I can only use the command line to compile the code. The code is quite large (maybe 100 files) and I need to update the include commands in many files. For when I try to compile it errors on for instance: #include <gsl/gsl_math.h> with a file cannot be found error. I am assuming it cannot be found because the location of the gsl folder was declared in one of the search directory field options in the IDE. I could go through each file an update to the correct path, but is there a better way of doing this for use with a makefile?
Thanks!
EDIT Makefile In Question
# -c : do not link, just create object file
# -o : output file name
CFLAGS += -c -O2 -I../ctraj -I../cspice/include -I../SGP4 -I../cconj -I../GSL-1.13/include
LIBS = -L../ctraj -lctraj -L../cspice/lib -lcspice -L../SGP4 -lsgp4 -L../cconj -lcconj -L./ -lgsl-0 -lgslcblas-0 -lm
DEPS = light.h ../ctraj/ctraj.h ../cconj/cconj.h
OBJ = light.o tle.o propagator.o orbitfit.o conjunction.o light_displacement.o forces_LF.o
OUT = light.exe
%.o: %.c $(DEPS)
gcc -o $# $< $(CFLAGS)
light: $(OBJ)
cd ../ctraj/; make
gcc -o $(OUT) $(OBJ) $(LIBS)
clean:
rm *.o $(OUT)
Edit 2
Folder Structure
light->(GSL-1.13, Light, cconj, ctraj)
the makefile is inside the Light folder.
Error Message
cd ../ctraj/; make
make[1]: Entering directory `/light/ctraj'
gcc -o forces.o forces.c -c -Wall -Wno-maybe-uninitialized -Wno-unused-but-set-variable -O2 -I../cspice/include -Inrlmsise
In file included from ../Light/../cconj/cconj.h:12:0,
from ../Light/light.h:13,
from forces.c:3:
../Light/../cconj/../GSL-1.13/include/gsl/gsl_blas.h:26:28: fatal error: gsl/gsl_vector.h: No such file or directory
compilation terminated.
make[1]: *** [forces.o] Error 1
make[1]: Leaving directory /light/ctraj'
make: *** [light] Error 2
EDIT 3
Second makefile in cconj
# -c : do not link, just create object file
# -o : output file name
#-L../cconj -lcconj
CFLAGS += -c -O2 -I./ -I../GSL-1.13/include
LIBS = -L./ -lgsl-0 -lgslcblas-0 -lm
INC= -I../GSL-1.13/include
DEPS = cconj.h
OBJ = cconj_util.o ellipse_intersect.o collision_prob_real.o rcs2size.o
OUT = libcconj.a
%.o: %.c $(DEPS)
gcc -o $# $< $(CFLAGS)
cconj: $(OBJ)
ar rcs $(OUT) $(OBJ)
clean:
rm *.o $(OUT)
Try adding this line to your makefile, and tell us if it works:
CFLAGS += -I../GSL-1.13/include
In order to compile source code and produce object files, Make must use a rule. (If you don't put such a rule in the makefile, Make has a default rule for that purpose.) It looks something like this:
%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
Without digging too deeply into how that works, we can say that CFLAGS is a list of arguments to be passed to the compiler. When we add -I../GSL-1.13/include, we tell the compiler "if you want to #include something and can't find it elsewhere, look in ../GSL-1.13/include".
If this approach doesn't work, then there's probably a rule in the makefile we must find and alter.
EDIT:
The problem isn't in this makefile (which already contains a reference to GSL-1.13/include). In this command:
cd ../ctraj/; make
this makefile launches a second Make process, which uses the Makefile in light/cconj/. According to the compiler output (gcc -o forces.o ...), that makefile does not include the reference. So try adding the same line there, and if that doesn't work, post that makefile and we'll keep looking.
Use -I option of gcc to specify where to look for includes.