MAKEFILE using Library : Linker command failed - c

Hello I can't make my Makefile working with
$(CC) $(CFLAGS) $(INC) $(OBJS) $(MLX_LNK) -o $(NAME).
got a
clang -O3 -Wall -Wextra -Werror -I -I cub3d.h src/cub3d.o src/checks/argvcheck.o src/checks/parse_map.o src/libft/basics.o src/libft/basics_bis.o src/libft/get_next_line.o src/utils/errors.o -L minilibx_opengl -lmlx -framework OpenGL -framework AppKit -o cub3D
clang: error: cannot specify -o when generating multiple output files
make: *** [cub3D] Error 1
The command on terminal I do is "make test1"
I also tried with $(CC) $(CFLAGS) -I $(HEADER) $(OBJS) $(MLX_LNK) -o $(NAME).
but got
Compiling...
clang -O3 -Wall -Wextra -Werror -I cub3d.h src/cub3d.o src/checks/argvcheck.o src/checks/parse_map.o src/libft/basics.o src/libft/basics_bis.o src/libft/get_next_line.o src/utils/errors.o -L minilibx_opengl -lmlx -framework OpenGL -framework AppKit -o cub3D
Undefined symbols for architecture x86_64:
"_init_cube", referenced from:
_init_game in cub3d.o
"_write_errors", referenced from:
_verify_line in argvcheck.o
_ft_parse_cub in argvcheck.o
_my_get_next_line in get_next_line.o
ld: symbol(s) not found for architecture x86_64
clang: error: linker command failed with exit code 1 (use -v to see invocation)
Many thanks for your help
Makefile here :
NAME = cub3D
HEADER = cub3d.h
CC = clang
CFLAGS = -O3 -Wall -Wextra -Werror
INC = -I $(MLX-DIR) -I $(HEADER)
MLX_DIR = minilibx_opengl
MLX_LNK = -L $(MLX_DIR) -lmlx -framework OpenGL -framework AppKit
SRCS = src/main.c \
src/checks/argvcheck.c \
src/libft/basics.c \
src/libft/get_next_line.c \
src/utils/errors.c \
OBJS = $(SRCS.c=.o)
all: $(NAME)
mlx: $(MLX-DIR)
#echo "\033[34m-= Making libX.a... =-"
#make -C $(MLX_DIR)
$(NAME): ${OBJS} mlx
$(CC) $(CFLAGS) $(INC) $(OBJS) $(MLX_LNK) -o $(NAME)
test1: $(NAME)
$(NAME) ; ./a.out maps/test1.cub
clean:
#echo "\033[0;31mCleaning..."
rm -f $(OBJS)
# + $(B_OBJ)
# + rm -f bitmap.bmp
#echo "\033[0m"
fclean: clean
#echo "\033[34m-= Cleaning mlx... =-"
#make clean -C $(MLX_DIR)
#echo "\033[0;31mRemoving executable..."
rm -f $(NAME)
#echo "\033[0m"
re: fclean all
.PHONY: all clean fclean re
````

Well, first of all this is wrong:
OBJS = $(SRCS.c=.o)
You're missing a : here, it should be $(SRCS:.c=.o) As a result, OBJS will be empty.
Next, this is not causing you problems at the moment but is not right: you should always use $(MAKE) never a raw command like make when invoking a sub-make.
Finally, the way you've written your question by embedding results into the middle of the makefile makes it very hard to read. Please put the makefile first, then separate sections for different attempts at recipes. And you need to include the command line that make printed out (cut and paste the exact line please!) for us to see what the command being run it (with all variables expanded). Typically it becomes VERY obvious what the problem is if you look at that.
For example in this case you'd see that there are actually no object files in the link line, so it should be clear that the $(OBJS) variable is not being set properly.
EDIT
OK, thanks for showing the command line. Now, you should look at it carefully and you will see your problem :). Look at this here:
clang -O3 -Wall -Wextra -Werror -I -I cub3d.h src/cub3d.o ...
Does that look right to you? Look specifically at -I -I cub3d.h... does that seem right?
What happens is that the compiler expects a pathname to come after the -I and there isn't one, so it treats the second -I as the pathname. Then the file cub3d.h is treated as a source file, and you can't link a source file with object files.
So why does this look like this? Look at your makefile:
INC = -I $(MLX-DIR) -I $(HEADER)
so the missing thing is where $(MLX-DIR) goes. What is that variable? Well you have this:
MLX_DIR = minilibx_opengl
but this is not the same thing because it uses an underscore whereas the reference uses a dash. So, make them the same.
Then you'll see that it's not valid to put a file as an argument to -I. That takes a directory to search for header files. If you want to include the header you have to add #include "cub3d.h" in your source code, not add it to the compile line.

Related

Makefiles giving the compiler files that dont/shouldnt exist

I have a basic Makefile setup for C OpenGL programming but when running there are 2 files passed to clang that shouldnt exist and i have no idea why. The problem happened after i added glad and glfw to the project.
code:
CC = clang
`CCFLAGS = -lGL -lglfw -std=c++20 -v -Wall -Wextra -Wepedantic -g -lgdi32
LDFLAGS = lib/glad/src/glad.o lib/glfw/src/libglfw3.a -lgdi32 -lm
SRC = $(wildcard src/*.c)
OBJ = $(SRC:.c=.o)
BIN = bin
all: libs build
libs:
cd lib/glad && $(CC) -o src/glad.o -Iinclude -c src/glad.c
cd lib/glfw && cmake . -G 'Unix Makefiles' && make
build: $(OBJ)
$(CC) -o $(BIN)/build $^ $(LDFLAGS)
%.o %.c:
$(CC) -o $# -c $< $(CCFLAGS)
run:
./bin/build.exe
ERROR:
clang: error: no such file or directory: 'all.o'
clang: error: no such file or directory: 'libs'
clang: error: no such file or directory: 'build'
When asking questions please include the command you typed, the command make printed, plus at least the first and last few lines of error messages (properly formatted as code blocks).
I'm assuming that the extra quote character is an error in your cut and paste; please take a moment to review your question after you post it (or even better, using the preview before you post it). You are writing this one time, but tens or hundreds of people will spend their time reading it. Please be considerate enough to make it easy for them.
Your problem is this:
%.o %.c:
$(CC) -o $# -c $< $(CCFLAGS)
You want to say "build a .o file from a .c file using this rule", but %.o %.c: says instead, "build both a .o and a .c file, from nothing, using this rule".
You need:
%.o: %.c
$(CC) -o $# -c $< $(CCFLAGS)

Add flags on Makefile compilation only if a parameter is given

I would like to know how the CFLAGS variable could be removed from the compilation and added when a parameter is given to the Makefile like "make cflags" without having to duplicate the compilation.
Here is a part of my Makefile :
EXE = $(PATH_EXE)/COLLECTEUR
all: ${EXE}
clean:
rm -f ${PATH_OBJ}/*.o
rm -f ${PATH_EXE}/*
clean_bin:
rm -f ${PATH_EXE}/*
link:
rm -f ${PATH_EXE}/*
$(PATH_EXE)/COLLECTEUR: $(PATH_OBJ)/Test.o $(OBJS)
${LD} ${CFLAGS} ${OBJS} $(PATH_OBJ)/Test.o ${LDFLAGS} -o $#
$(PATH_OBJ)/%.o : %.c
${CC} ${CFLAGS} $< -o $#
The general trick in make is to use a feature known as a target specific variable, which allows you to set or append to variables if a specific target is given, like so:
cflags: CFLAGS+=-Wall -Werror
cflags: all
What this says is for the target cflags append -Wall -Werror to the cflags, and the following line says that the cflags target depends on the all target.
Now, I did notice some errors in your compilation options.
The final link line ${LD} will invoke ld, which doesn't take ${CFLAGS} by default, you're probably better off using the compiler driver there as well (replace the ${LD} with ${CC}).
The compilation line for $(PATH_OBJ)/%.o files compiles and links the files, because it's missing the -c option, which instructs the compiler to compile only, and not to link.

Handling #include <folder/file.h> in C with makefiles

I am in the process of porting some code that was developed in the codeblocks IDE. I am transferring it to a Linux server where I can only use the command line to compile the code. The code is quite large (maybe 100 files) and I need to update the include commands in many files. For when I try to compile it errors on for instance: #include <gsl/gsl_math.h> with a file cannot be found error. I am assuming it cannot be found because the location of the gsl folder was declared in one of the search directory field options in the IDE. I could go through each file an update to the correct path, but is there a better way of doing this for use with a makefile?
Thanks!
EDIT Makefile In Question
# -c : do not link, just create object file
# -o : output file name
CFLAGS += -c -O2 -I../ctraj -I../cspice/include -I../SGP4 -I../cconj -I../GSL-1.13/include
LIBS = -L../ctraj -lctraj -L../cspice/lib -lcspice -L../SGP4 -lsgp4 -L../cconj -lcconj -L./ -lgsl-0 -lgslcblas-0 -lm
DEPS = light.h ../ctraj/ctraj.h ../cconj/cconj.h
OBJ = light.o tle.o propagator.o orbitfit.o conjunction.o light_displacement.o forces_LF.o
OUT = light.exe
%.o: %.c $(DEPS)
gcc -o $# $< $(CFLAGS)
light: $(OBJ)
cd ../ctraj/; make
gcc -o $(OUT) $(OBJ) $(LIBS)
clean:
rm *.o $(OUT)
Edit 2
Folder Structure
light->(GSL-1.13, Light, cconj, ctraj)
the makefile is inside the Light folder.
Error Message
cd ../ctraj/; make
make[1]: Entering directory `/light/ctraj'
gcc -o forces.o forces.c -c -Wall -Wno-maybe-uninitialized -Wno-unused-but-set-variable -O2 -I../cspice/include -Inrlmsise
In file included from ../Light/../cconj/cconj.h:12:0,
from ../Light/light.h:13,
from forces.c:3:
../Light/../cconj/../GSL-1.13/include/gsl/gsl_blas.h:26:28: fatal error: gsl/gsl_vector.h: No such file or directory
compilation terminated.
make[1]: *** [forces.o] Error 1
make[1]: Leaving directory /light/ctraj'
make: *** [light] Error 2
EDIT 3
Second makefile in cconj
# -c : do not link, just create object file
# -o : output file name
#-L../cconj -lcconj
CFLAGS += -c -O2 -I./ -I../GSL-1.13/include
LIBS = -L./ -lgsl-0 -lgslcblas-0 -lm
INC= -I../GSL-1.13/include
DEPS = cconj.h
OBJ = cconj_util.o ellipse_intersect.o collision_prob_real.o rcs2size.o
OUT = libcconj.a
%.o: %.c $(DEPS)
gcc -o $# $< $(CFLAGS)
cconj: $(OBJ)
ar rcs $(OUT) $(OBJ)
clean:
rm *.o $(OUT)
Try adding this line to your makefile, and tell us if it works:
CFLAGS += -I../GSL-1.13/include
In order to compile source code and produce object files, Make must use a rule. (If you don't put such a rule in the makefile, Make has a default rule for that purpose.) It looks something like this:
%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $#
Without digging too deeply into how that works, we can say that CFLAGS is a list of arguments to be passed to the compiler. When we add -I../GSL-1.13/include, we tell the compiler "if you want to #include something and can't find it elsewhere, look in ../GSL-1.13/include".
If this approach doesn't work, then there's probably a rule in the makefile we must find and alter.
EDIT:
The problem isn't in this makefile (which already contains a reference to GSL-1.13/include). In this command:
cd ../ctraj/; make
this makefile launches a second Make process, which uses the Makefile in light/cconj/. According to the compiler output (gcc -o forces.o ...), that makefile does not include the reference. So try adding the same line there, and if that doesn't work, post that makefile and we'll keep looking.
Use -I option of gcc to specify where to look for includes.

How can I write Makefile (with sub Makfile ) more concise

When I do practice , I have a practice path.
Under this path , I have an Include path named myInclude (I have some useful function is this folder and I always use it.)
And a code path named symbol_try.I always make add new folder (with a c file and main function in it) in symbol_try and compile it.
Each time I have to compile it by gcc in terminal .Its a boring work , so I write a Makefile.
Here is an example:
the main Makefile in practice path:
FOBJS=
include myInclude/Rule.mk
include symbol_try/codeList_13.1/Rule.mk
symbol:$(FOBJS) <==What exactly I what . A executable file.
gcc -o symbol $(FOBJS) -pthread -lpthread
subsystem:
cd myInclude/ && $(MAKE)
cd symbol_try/codeList_13.1/ &&$(MAKE)
clean:
rm -rf symbol
In the myInclude/Rule.mk
FOBJS+=myInclude/otherFunction.o myInclude/error.o \
myInclude/unit.o myInclude/unitTest.o\
In the symbol_try/codeList_13.1/Rule.mk
FOBJS+=symbol_try/codeList_13.1/codeList_13.1.o
In myInclude/Makefile:
OBJS=otherFunction.o error.o unit.o unitTest.o
ALL:$(OBJS)
.PHONY:ALL
$(OBJS):%.o:%.c
gcc -c $< -o $#
clean :
otherFunction.o error.o unit.o
In symbol_try/codeList_13.1/Makefile:
codeList_13.1.o:codeList_13.1.c
gcc -c codeList_13.1.c
Well.That can work. But as you see , I have to write a Rule.mk(to initialize the FOBJS) and a Makefile for each folder.
I am new for make , I want find a way more concise , witch I only need write one Makefile for each folder and a main Makefile.No Rule.mk any more.
PS: I always change the code in myInclude ,so I don't want to build it a library.
Thanks for any help.
Here's one way you can do it with just one Makefile:
CC = gcc
CPPFLAGS += -I myInclude/ (1)
CFLAGS += -std=c99 -Wall (2)
VPATH = myInclude/ \ (3)
symbol_try/codeList_13.1/
symbol: otherFunction.o error.o unit.o unitTest.o codeList_13.1.o (4)
$(CC) -o $# $^ (5)
.PHONY : clean
clean:
rm -f symbol *.o
Note that make knows how to build C files and has some standard macros: CC, CPPFLGAS, CFLAGS
Add the include paths of your headers. You presumably have some headers for the individual object files in the myInclude directory.
Put the compiler flags here.
Add the paths to the source files you want to build.
List the object files that the executable depends upon
As there is no file called symbol.c you need to tell make how to create symbol.o with a rule. $# means the target ('symbol', here), and $^ means all of the prerequisites (the object files listed).
Here's a list of all of the files in my test directories for this:
$ find . -type f
.
./Makefile
./myInclude/error.c
./myInclude/header.h
./myInclude/otherFunction.c
./myInclude/unit.c
./myInclude/unitTest.c
./symbol_try/codeList_13.1/codeList_13.1.c
And the build output:
$ make
gcc -std=c99 -Wall -I myInclude/ -c -o otherFunction.o myInclude/otherFunction.c
gcc -std=c99 -Wall -I myInclude/ -c -o error.o myInclude/error.c
gcc -std=c99 -Wall -I myInclude/ -c -o unit.o myInclude/unit.c
gcc -std=c99 -Wall -I myInclude/ -c -o unitTest.o myInclude/unitTest.c
gcc -std=c99 -Wall -I myInclude/ -c -o codeList_13.1.o symbol_try/codeList_13.1/codeList_13.1.c
gcc -o symbol otherFunction.o error.o unit.o unitTest.o codeList_13.1.o
Why don't you create a library from the objects in myInclude and do the linking in the Makefile in your code path (symbol_try/codeList_13.1). The latter is better anyway because the needed libraries (-pthread -lpthread in your case) might change as well for some other code.
The main Makefile now would have got nothing to do but call make in all needed subdirectories.
In each folder have a makefile with
SOURCES=sample.c sampletest.c
OBJECTS=$(SOURCES:%.c=$(OBJDIR)/%.o)
all: $(OBJECTS)
$(OBJDIR)/%.o: %.c
$(CC) $(CFLAGS) -o $# $<
In the root directory of a project, create a makefile with a rule to compile every sub-folder like the below.
Dirs= path-to-rootdir
objs:
set -e ; \
for i in $(Dirs) ; do \
$(MAKE) CC="$(CC)" CFLAGS="$(CFLAGS_MODULE)" LDFLAGS="$(LDFLAGS)" OBJDIR="$(OBJDIR)" -C $$i; \
done
And then you could use it build the executable by adding a rule
EXE: objs
$(CC) -L./Path1 $(LIB_PATH) -llib1 -o $(EXE_NAME) $(wildcard $(OBJDIR)/*.o)
Hope this helps!!!

A Makefile with Multiple Executables

I am trying to write a makefile which uses macros to create multiple executables from multiple files at once. I tried searching through previously answered questions but, because I am fairly new to programming in C as well as working with gcc, I was not able to find an answer to my question.
Here is what I have so far:
CC=gcc
CFLAGS=-I.
OBJ = ex1.c ex3.c
EXECUTABLE = ex1 ex3
$(EXECUTABLE): $(OBJ)
gcc -o $# $^ $(CFLAGS)
clean:
rm -f $(EXECUTABLE)
I would like the line
$(EXECUTABLE): $(OBJ)
to create executables ex1 and ex3 from files ex1.c ex3.c respectively.
For this particular case, where each executable has a single source file with .c extension, all you need is a one line Makefile:
all: ex1 ex3
The built-in default rules for make then work already:
$ make
cc -O2 -pipe ex1.c -o ex1
cc -O2 -pipe ex3.c -o ex3
Behind the scene, make is using the POSIXly mandated built-in single suffix rule
.c:
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $<
Vary the command to your liking with make CC=gcc CFLAGS=-O2 LDFLAGS=-s and similar.
Trivia of the day: in fact, if you are willing to name the targets when invoking make, you can use an empty or even run without any Makefile:
$ make -f /dev/null CC=gcc CFLAGS=-O2 LDFLAGS=-s ex1 ex3
gcc -O2 -s ex1.c -o ex1
gcc -O2 -s ex3.c -o ex3
$ rm -f Makefile ex1 ex3
$ make CC=gcc CFLAGS=-O2 LDFLAGS=-s ex1 ex3
gcc -O2 -s ex1.c -o ex1
gcc -O2 -s ex3.c -o ex3
Make magic!
As a rule of thumb, don't reinvent the wheel (or rules), use the rules that are already there. It simplifies your and make's life a lot. This makes for small and sexy makefiles to impress the ladies with :-)
Some suggestions (assuming you use GNU make, not something else)
First, run once make -p, you'll understand what builtin rules make is knowing. Look in particular for COMPILE.c and LINK.c
Then, I suggest
CFLAGS= -g -Wall -I.
(because you really want -g for debugging, and -Wall to get most warnings)
And you probably don't need
$(EXECUTABLE): $(OBJ)
gcc -o $# $^ $(CFLAGS)
However, I suggest adding before most other rules
.PHONY: all clean
all: $(EXECUTABLES)
Actually, I would code your Makefile (for GNU make!) as follow
# file Makefile
CC= gcc
RM= rm -vf
CFLAGS= -Wall -g
CPPFLAGS= -I.
SRCFILES= ex1.c ex2.c ## or perhaps $(wildcard *.c)
OBJFILES= $(patsubst %.c, %.o, $(SRCFILES))
PROGFILES= $(patsubst %.c, %, $(SRCFILES))
.PHONY: all clean
all: $(PROGFILES)
clean:
$(RM) $(OBJFILES) $(PROGFILES) *~
## eof Makefile
Remember that tab is a significant character in Makefile-s (action part of rules). In this answer, lines starting with four spaces at least should really start with a tab character.
Once everything is debugged consider running make clean to clean everything, and then make -j CFLAGS=-O2 all to compile in parallel everything with optimizations.
At last, I recommend using remake and running remake -x to debug complex Makefile-s
Of course, I'm supposing that your directory has only single-file programs.
BTW, there are other build automation tools. Perhaps you might consider using omake or ninja. For building large programs (millions of source code lines) consider also automake, ccache, cmake, icecream. In some cases, consider generating some C code with GPP, GNU bison, SWIG, etc... or using your own Python or Guile script (or C meta-program). See also this draft report.
Don't forget to use a version control system like git for your source files. It is also time to learn such a tool.
The following answer includes multiple executable such as initiate, process1, process2, ..., process4.
LOCAL_INCLUDE=./
all: clean process_first process_second init
process_first:
gcc -g -o process1 -I$(LOCAL_INCLUDE) process1.c -lzmq -L. -L./.
gcc -g -o process2 -I$(LOCAL_INCLUDE) process2.c -lzmq -L. -L./.
process_second:
gcc -g -o process3 -I$(LOCAL_INCLUDE) process3.c -lzmq -L. -L./.
gcc -g -o process4 -I$(LOCAL_INCLUDE) process4.c -lzmq -L. -L./.
init:
gcc -g -o initiate -I$(LOCAL_INCLUDE) initiate.c -lzmq -lconfig -lpthread -L. -L./. -ldl -lrt
clean:
rm -rf init_manager.o init_manager
rm -rf process1 process2 process3 process4
NOTE: It is a good practice to clean and touch all the executable files before making them again.
You're close, but you need a pattern rule:
$(EXECUTABLE): % : %.c
And then a default rule to make it build both:
all: $(EXECUTABLE)

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