how to do acircular shift for an array via verilog - arrays

Question

In C language, there is an array x[0], x[1], ..., x[127], for a given number k in [0, 127), we difine left shift operation as y[n] = x[(n+k)%128], for n=0,1,2...,127
Now I am try to implement this in FPGA, as there are so many this type operations, I like to get the result as fast as possile.
I did this as follows,
module LEFT_SHIFT(
input clk,
input rst,
input [31:0] data_in[0:127])
input [6:0] shift,
output reg [31:0] data_ou[0:127]
);
integer i;
always # (posedge clk)
begin
if (rst)
for (i=0;i<128;i++)
data_out[i] <= 32'bb0;
else
for (i=0;i<128;i++)
data_out[(i+shift)%128] = data_in[i];
end
endmodule
Is this code fine in terms speed, resource and timing? I looks like a RAM, but RAM does't output all the memory at the same time.
Many thanks,
Jerry

Answer 1

If you replace the Mod operator (%) with a replication of the input data to make the circular shift you could make the task easier for the compiler. I tried this on the synthesis tool from a major ASIC tool vendor and the results were quite different.
if (rst)
for (integer i=0;i<128;i++)
data_out[i] <= 32'b0;
else begin
logic [31:0] tmp [0:255];
for (integer i=0;i<128;i++) begin
// replicate input data
tmp[i] = data_in[i];
tmp[i+128] = data_in[i];
end
for (integer i=0;i<128;i++)
data_out[i] <= tmp[128-shift+i];
end

Answer 2

That's a huge mux that will consume a lot of logic resources in the FPGA. I've seen things like that crash the tools before. You may want to consider adding more than just one register in there.
As far as speed, resource, and timing goes, it depends on how fast you want it to run and how many free resources you have. It could be fine at low speed on a big FPGA or impossible at higher speeds or small/full FPGA. But there's no need to speculate about resource and timing, just build it and see what happens.