How to refresh/update a variable in Makefile? - c

Question

I have this Makefile:
CFLAGS = -ffreestanding -O2 -nostdlib -lgcc
BUILD_DIR = ../build
BIN = $(BUILD_DIR)/os.bin
LINKER_SCRIPT = linker.ld
OBJ_FILES := $(shell find $(BUILD_DIR) -iname '*.o')
.PHONY: all
all:
#make -C boot
#make -C kernel
$(CC) -T $(LINKER_SCRIPT) -o $(BIN) $(CFLAGS) $(OBJ_FILES)
After compiling (doing make in boot and kernel directories) there should be files with .o extension, however OBJ_FILES is empty. Only after calling make again OBJ_FILES contains the .o files paths which are needed to link. So my question is how do I update OBJ_FILES after compiling in the boot and kernel directories, because OBJ_FILES doesn't update/refresh.

Answer 1

Let's say you have following structure:
.
|-- Makefile
|-- boot
| |-- Makefile
| |-- boot.c
| `-- boot.h
|-- kernel
| |-- Makefile
| |-- kernel.c
| `-- kernel.h
`-- main.c
and your Makefile looks like this
location = $(CURDIR)
OBJ_FILES = $(shell find $(location) -name '*.o')
all: make_common
gcc -o main main.c $(OBJ_FILES)
make_common:
#make -C boot
#make -C kernel
clean:
-rm boot/boot.o
-rm kernel/kernel.o
Your source code is quite simple:
> cat boot/boot.h
int boot();
> cat boot/boot.c
int boot() {
return 1;
}
> cat kernel/kernel.h
int kernel();
> cat kernel/kernel.c
int kernel() {
return 2;
}
> cat main.c
#include "boot/boot.h"
#include "kernel/kernel.h"
int main() {
int result = boot() + kernel();
return 0;
}
"inner" Makefiles contain
> cat boot/Makefile
all:
gcc -c boot.c
> cat kernel/Makefile
all:
gcc -c kernel.c
you will get what you are looking for
> make clean
rm boot/boot.o
rm: boot/boot.o: No such file or directory
make: [clean] Error 1 (ignored)
rm kernel/kernel.o
rm: kernel/kernel.o: No such file or directory
make: [clean] Error 1 (ignored)
> make
gcc -c boot.c
gcc -c kernel.c
gcc -o main main.c ..../boot/boot.o ..../kernel/kernel.o
VAR = val
Expanded when the variable is used.

Answer 2

So my question is how do I update OBJ_FILES after compiling in the boot and kernel directories, because OBJ_FILES doesn't update/refresh.
OBJ_FILES variable won't change its value once make started executing the rules.
See 3.7 How make Reads a Makefile for full details:
GNU make does its work in two distinct phases. During the first phase it reads all the makefiles, included makefiles, etc. and internalizes all the variables and their values and implicit and explicit rules, and builds a dependency graph of all the targets and their prerequisites. During the second phase, make uses this internalized data to determine which targets need to be updated and run the recipes necessary to update them.
It’s important to understand this two-phase approach because it has a direct impact on how variable and function expansion happens; this is often a source of some confusion when writing makefiles.
What you can do instead is restart make once it built kernel and boot:
all: $(BIN)
$(BIN) : $(OBJ_FILES)
$(CC) -T $(LINKER_SCRIPT) -o $# $(CFLAGS) $(OBJ_FILES)
Makefile :
#$(MAKE) -C boot
#$(MAKE) -C kernel
touch $# # <---- Causes the Makefile to be re-read.
.PHONY: all