Adjust Makefile to only recompile files if they have changed - c

I have a question regarding my Makefile. The Makefile intends to compile C files containing code for a STM8 µC using the Cosmic compiler. The problem is that everytime I invoke the build target, all available source file are getting recompiled without any change. I'm really new in the field of Makefiles and I have no idea how to fix it.
The second questions is related to the two targets "%.o: src/%.c" and %.o: src/stm8/%.c. They do exactly the same and I would prefer a generic one that is able to deal with all subdirectories within the src folder. With this solution it ist required to add an additional rule for each subfolder of the src folder
#***************PROJECT INFORMATIONS****************
PROJECT_NAME = stm8template
MODULES = stm8
#****************SET BUILD MODE*********************
ifeq ($(MODE), )
MODE=Debug
endif
#***************DIRECTORY INFORMATION***************
SRCDIR = src
INCLUDES = includes
OUTPUT_DIR = bin/$(MODE)
#**************HELPER FUNCTIONS*********************
rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))
#***************FILE SPECIFICATIONS***************
SOURCE_FILES = $(foreach d, $(call rwildcard,$(SRCDIR),*.c), $(notdir $d))
OBJECT_FILES = $(patsubst %.c, %.o, $(SOURCE_FILES))
HEADER_FILES = $(wildcard $(INCLUDES)/*.h) $(wildcard $(INCLUDES)/**/*.h)
INCLUDE_DIRS_PARAM=$(foreach d, $(MODULES), -iincludes/$d) -iincludes -iC:\Hstm8
#***************COMPILER INFORMATIONS***************
CC = cxstm8
LIBS = -l +mods0
ifeq ("$(MODE)","Debug")
CFLAGS = $(INCLUDE_DIRS_PARAM) -cl$(OUTPUT_DIR) -co$(OUTPUT_DIR) -pxp -no -pp +debug
else
CFLAGS = $(INCLUDE_DIRS_PARAM) -cl$(OUTPUT_DIR) -co$(OUTPUT_DIR) -pxp -no -pp
endif
#***************LINKER INFORMATIONS***************
LINKFILE=$(OUTPUT_DIR)\$(PROJECT_NAME).lkf
OUTFILE=$(PROJECT_NAME)
LFLAGS = -lC:\Lib
#*************FLASHER CONFIGURATIONS***************
FLASHER_PATH="C:\Program Files (x86)\STMicroelectronics\st_toolset\stvp\STVP_CmdLine.exe"
DEVICE=STM8S105x6
PORT=USB
PROG_MODE=SWIM
BOARD_NAME=ST-LINK
FLASHER_PARAM = -no_loop
#***************BUILT TARGETS***************
all: build run
%.o: src/%.c
$(info ********** Compile $< ***********)
$(CC) $(CFLAGS) $(LIBS) $<
%.o: src/stm8/%.c
$(info ********** Compile $< ***********)
$(CC) $(CFLAGS) $(LIBS) $<
build: $(OBJECT_FILES)
$(info ********** Build the Application ***********)
clnk -m $(OUTPUT_DIR)\$(OUTFILE).map -o $(OUTPUT_DIR)\$(OUTFILE).sm8 $(LINKFILE)
cvdwarf $(OUTPUT_DIR)\$(OUTFILE).sm8
chex -o $(OUTPUT_DIR)\$(OUTFILE).s19 $(OUTPUT_DIR)\$(OUTFILE).sm8
run:
$(info ********** Flashing the Application ***********)
$(FLASHER_PATH) -BoardName=$(BOARD_NAME) -Device=$(DEVICE) -Port=$(PORT) -ProgMode=$(PROG_MODE) -FileProg="$(OUTPUT_DIR)\$(OUTFILE).s19" $(FLASHER_PARAM)

The build target never gets created, so the commands after it are executed every time you run make (or make all or make build), so the program is linked each time.
Change your build target so that it is phony:
.PHONY: build clean
and so that it depends on the program, not the object files:
build: $(OUTPUT_DIR)\$(OUTFILE).sm8
and then have a rule (recipe) that builds the program if the object files are more recent:
$(OUTPUT_DIR)\$(OUTFILE).sm8: $(OBJECT_FILES)
$(info ********** Build the Application ***********)
clnk -m $(OUTPUT_DIR)\$(OUTFILE).map -o $(OUTPUT_DIR)\$(OUTFILE).sm8 $(LINKFILE)
cvdwarf $(OUTPUT_DIR)\$(OUTFILE).sm8
chex -o $(OUTPUT_DIR)\$(OUTFILE).s19 $(OUTPUT_DIR)\$(OUTFILE).sm8
It isn't 100% clear to me that I chose the correct suffix for the program. I would also create series of macros to avoid the repetition I see:
OUTFILE.sm8 = $(OUTPUT_DIR)\$(OUTFILE).sm8
OUTFILE.s19 = $(OUTPUT_DIR)\$(OUTFILE).s19
OUTFILE.map = $(OUTPUT_DIR)\$(OUTFILE).map
build: $(OUTFILE.sm8)
$(OUTFILE.sm8): $(OBJECT_FILES)
$(info ********** Build the Application ***********)
clnk -m $(OUTFILE.map) -o $(OUTFILE.sm8) $(LINKFILE)
cvdwarf $(OUTFILE.sm8)
chex -o $(OUTFILE.s19) $(OUTFILE.sm8)
Also, since I work on Unix mostly, I'd use / instead of \, but that's a minor detail.

Update:
Thank you all for your help. I changed the Makefile in the way shown below. The second problem is now fixed but the first problem still remains.
Every time the build rule is invoked all .c files are recompiled. Compiling only the changed files is the main purpose/benefit of using make, I thought. So something is wrong but unfortunately I don't find the mistake.
#***************PROJECT INFORMATIONS****************
PROJECT_NAME = stm8template
MODULES = stm8
#****************SET BUILD MODE*********************
ifeq ($(MODE), )
MODE=Debug
endif
#***************DIRECTORY INFORMATION***************
SRCDIR = src
INCLUDES = includes
#**************HELPER FUNCTIONS*********************
rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))
#***************FILE SPECIFICATIONS***************
SOURCE_FILES = $(foreach d, $(call rwildcard,$(SRCDIR),*.c), $(notdir $d))
OBJECT_FILES = $(patsubst %.c, %.o, $(call rwildcard,$(SRCDIR),*.c))
HEADER_FILES = $(wildcard $(INCLUDES)/*.h) $(wildcard $(INCLUDES)/**/*.h)
INCLUDE_DIRS_PARAM=$(foreach d, $(MODULES), -iincludes/$d) -iincludes -iC:\Hstm8
#***************COMPILER INFORMATIONS***************
CC = cxstm8
LIBS = -l +mods0
ifeq ("$(MODE)","Debug")
CFLAGS = $(INCLUDE_DIRS_PARAM) -cl$(OUTPUT_DIR) -co$(OUTPUT_DIR) -pxp -no -pp +debug
else
CFLAGS = $(INCLUDE_DIRS_PARAM) -cl$(OUTPUT_DIR) -co$(OUTPUT_DIR) -pxp -no -pp
endif
#***************LINKER INFORMATIONS***************
LINKFILE=$(OUTPUT_DIR)\$(PROJECT_NAME).lkf
LFLAGS = -LC:\Lib
#*******************OUTPUT FILES********************
OUTPUT_DIR = bin/$(MODE)
OUTFILE=$(PROJECT_NAME)
OUTFILE.sm8 = $(OUTPUT_DIR)\$(OUTFILE).sm8
OUTFILE.s19 = $(OUTPUT_DIR)\$(OUTFILE).s19
OUTFILE.map = $(OUTPUT_DIR)\$(OUTFILE).map
TARGET_FILE=$(OUTPUT_DIR)\$(PROJECT_NAME).elf
#*************FLASHER CONFIGURATIONS***************
FLASHER_PATH="C:\Program Files (x86)\STMicroelectronics\st_toolset\stvp\STVP_CmdLine.exe"
DEVICE := STM8S105x6
PORT=USB
PROG_MODE=SWIM
BOARD_NAME=ST-LINK
FLASHER_PARAM = -no_loop
#***************BUILT TARGETS***************
.PHONY: all run build clean
all: build run
%.o: %.c
$(info ********** Compile $< ***********)
$(CC) $(CFLAGS) $(LIBS) $<
build: $(OUTPUT_DIR)\$(PROJECT_NAME).elf
$(TARGET_FILE): $(OBJECT_FILES)
$(info ********** Build the Application ***********)
clnk -m $(OUTFILE.map) -o $(OUTFILE.sm8) $(LINKFILE)
cvdwarf $(OUTFILE.sm8)
chex -o $(OUTFILE.s19) $(OUTFILE.sm8)
run:
$(info ********** Flashing the Application ***********)
$(FLASHER_PATH) -BoardName=$(BOARD_NAME) -Device=$(DEVICE) -Port=$(PORT) -ProgMode=$(PROG_MODE) -FileProg="$(OUTPUT_DIR)\$(OUTFILE).s19" $(FLASHER_PARAM)

Related

Makefile Stops Building Files After First .o In Out-of-Source Build

I have a bit of a huge Makefile that basically works as I want it to.
Issue: The problem I'm having is that the makefile only checks if the first .o needs updating and not if any others do. I'm not sure what part of my makefile is in error.
Context: I have project structure like this:
quendor
src
main.c
options.c
quendor.h
Makefile
When my Makefile builds, it constructs a build directory and things look as follows:
quendor
build
src
main.d
main.o
options.d
options.o
src
main.c
options.c
quendor.h
Makefile
To See the Problem: Now let's say I don't change my main.c but I do change my options.c file. In that case, when I run make again I get this:
make: 'build/./src/main.o' is up to date.
I'm not sure if this is because it's building into a build/src directory rather than just build as I intended.
Here is the full Makefile and I'm including all of it just because I'm not sure what might be a problem and I don't want to make unwarranted assumptions.
.PHONY : all clean
NAME := quendor
PLATFORM := windows
CC := gcc
LINK := gcc
BUILD_DIR ?= ./build
SRC_DIR ?= ./src
ifeq ($(PLATFORM), windows)
TARGET ?= quendor.exe
else
TARGET ?= quendor
endif
ifeq ($(CC), gcc)
CFLAGS += -std=c11 -Wall -Wextra -Wpedantic -Wconversion -Wmissing-prototypes -Wshadow -MMD -MP
LDFLAGS +=
OPT +=
endif
SRCS := $(wildcard $(SRC_DIR)/*.c)
OBJS := $(SRCS:%.c=$(BUILD_DIR)/%.o)
DEPS := $(OBJS:%.o=%.d)
MKDIR_P ?= #mkdir -p $(dir $#)
-include $(DEPS)
all : $(TARGET)
#echo "Building $(TARGET)"
$(TARGET) : $(OBJS)
$(LINK) $(OPT) -o $# $^ $(LDFLAGS)
$(BUILD_DIR)/%.o : %.c
$(MKDIR_P)
$(CC) $(CFLAGS) -c $< -o $#
clean:
$(RM) $(TARGET) -r $(BUILD_DIR)
This may be an artifact of how StackOverflow is parsing my Makfile but I do notice that it's showing different syntax highlighting after this line:
SRCS := $(wildcard $(SRC_DIR)/*.c)
The problem is that you are including the dependencies before you define the all rule:
-include $(DEPS)
all : $(TARGET)
If you don't specify a particular target to build on the command line (e.g., if you don't run make all) then make chooses the first explicit target in the makefile (and any included makefiles!!) as the target to build.
I assume that the dependency definitions in the $(DEPS) variable define main.o as a target and since that comes before all, it's the only thing that's run by default.
Move the -include statement later in the makefile (I typically put these all at the end of the makefile) and it will work.

Multiple compilations with makefile

I've been having serious trouble with Makefiles, I'm trying to run those commands in it and so far most of the changes I made resulted in "Nothing to be done for 'all'" no matter I change the lines, it just don't work. For example, PROG4 should have worked below but it says nothing to be done.
BIN_DIR = bin
LEX_DIR = lexyacc-code
LIB_DIR = lib
SRC_DIR = src
OBJ_DIR = obj
CC = gcc
BS = bison
FX = flex
CFLAGS = -I$(LIB_DIR)
SRCS = $(wildcard $(LEX_DIR)/calc3b.c)
SRCS2 = $(wildcard $(LEX_DIR)/calc3.y)
SRCS3 = $(wildcard $(LEX_DIR)/calc3.l)
SRCS4 = $(wildcard $(OBJ_DIR)/y.tab.c)
SRCS5 = $(wildcard $(OBJ_DIR)/lex.yy.c)
OBJS = $(patsubst $(LEX_DIR)/%.c,$(OBJ_DIR)/%.o,$(SRCS))
PROG = calc3b
PROG2 = y.tab
RM = rm -f
MVV="$(shell mv y.tab.c obj)"; echo $MVV
all: $(PROG2) $(PROG4)
$(PROG): $(OBJS)
$(CC) $^ -o $(PROG)
$(PROG2):
$(BS) -y -d $(SRCS2)
$(PROG4): $(CC) -c $(SRCS4) $(SRCS5) $(CFLAGS)
$(OBJ_DIR)/%.o: $(LEX_DIR)/%.c
$(CC) $(CFLAGS) -c $< -o $#
clean:
$(RM) $(PROG) $(OBJS)
Only PROG2 is working, basically for result I have header and source file which I tried to move specific folders but eventually I did it with 'mv' command (I know its against Makefile).
The commands are these:
bison -y -d calc3.y
flex calc3.l
gcc -c y.tab.c lex.yy.c
gcc y.tab.o lex.yy.o calc3b.c -o calc3b.exe
First command, I have one header and source as a result.
Second I have one source as a result.
Third I have 2 objects file as a result.
And fourth, I will have one executable.
Therefore, I also need to move those files to their specific folders.
Can anyone help me out with this? Thanks.
I think that the problem with $(PROG4) is that you forgot to put command on a new line with tab. In what you've showed above, the whole line of command is placed where it should be dependency but not command. Therefore, makefile executes no command for $(PROG4).

Make: *.h no such file or directory

My project has the following directory structure:
main.cu
FA_kernels/*.cu
FD_kernels/*.cu
MEM_kernels/*.cu
MOD_kernels/*.cu
headers/*.h
Where *.extension means a bunch of files with that extension. I can't seem to get the makefile to work correctly. The error I'm getting is:
FA_kernels/FA_SFD.cu:2:20: fatal error: FA_SFD.h: No such file or directory
#include "FA_SFD.h"
^
My intent was for -I headers to be specified to the compiler, thereby making the headers directory available for searching. Clearly this has not worked. Here is the makefile:
CC := nvcc
LD := nvcc
MODULES := FA_kernels FD_kernels MEM_kernels MOD_kernels .
SRC_DIR := $(MODULES)
BUILD_DIR := $(addprefix build/,$(MODULES))
SRC := $(foreach sdir,$(SRC_DIR),$(wildcard $(sdir)/*.cu))
OBJ := $(patsubst src/%.cu,build/%.o,$(SRC))
INCLUDES := $(addprefix -I,headers)
vpath %.cu $(SRC_DIR)
define make-goal
$1/%.o: %.cu
$(CC) $(INCLUDES) -c $$< -o $$#
endef
.PHONY: all checkdirs clean
all: checkdirs build/lem
build/lem: $(OBJ)
$(LD) $^ -o $#
checkdirs: $(BUILD_DIR)
$(BUILD_DIR):
#mkdir -p $#
clean:
#rm -rf build
$(foreach bdir,$(BUILD_DIR),$(eval $(call make-goal,$(bdir))))
Any ideas?
UPDATE: Here is the full console output from running make
nvcc FA_kernels/FA_SFD.cu FA_kernels/partition.cu FA_kernels/contribA.cu FA_kernels/parallel-SFD-List.cu FD_kernels/SFD.cu FD_kernels/flow_routines.cu FD_kernels/floodingDriver.cu FD_kernels/watershed.cu MEM_kernels/memory_dev.cu MEM_kernels/Data.cu MEM_kernels/MapInfo.cu MEM_kernels/memory.cu MOD_kernels/erosion.cu MOD_kernels/eroincidep.cu MOD_kernels/updates.cu MOD_kernels/runoffweight.cu MOD_kernels/depo-List.cu lem.cu -o build/lem
FA_kernels/FA_SFD.cu:2:20: fatal error: FA_SFD.h: No such file or directory
#include "FA_SFD.h"
^
compilation terminated.
Makefile:24: recipe for target 'build/lem' failed
make: *** [build/lem] Error 1
From your output, apparently patsubst in OBJ was not successful at all. From the way you define SRC, I assume makefile is directly under src/, then you should change src/%.cu to %.cu in the definition of OBJ as such:
OBJ := $(patsubst %.cu,build/%.o,$(SRC))
Also, if I understand you correctly, you were trying to create a folder structure under build/ that is identical to the folder structure under src/. So, for instance, /src/abc.cu will generate /src/build/abc.o, then you don't need to define functions to get these rules, simply do:
build/%.o: %.cu
$(CC) $(INCLUDES) -c $< -o $#
and you are good to go.
If instead you wish to create build/ on the same level as src/. i.e. XXX/src/abc.cu -> XXX/build/abc.o. Then simply replace all occurrences of build in your makefile with ../build.
If you would rather put makefile at the same level as src/, then you should edit SRC to reflect that:
SRC := $(foreach sdir,$(SRC_DIR),$(wildcard src/$(sdir)/*.cpp))
and change the target to:
build/%.o: src/%.cpp
$(CC) $(INCLUDES) -c $< -o $#
Now you can safely remove vapth ... and the last line $foreach in your makefile.
EDIT: This is what your makefile will look like. I can't test it right now so there may be some mistakes in it, but hopefully it makes you understand the general idea.
CC := nvcc
LD := nvcc
MODULES := FA_kernels FD_kernels MEM_kernels MOD_kernels .
SRC_DIR := $(MODULES)
BUILD_DIR := $(addprefix build/,$(MODULES))
SRC := $(foreach sdir,$(SRC_DIR),$(wildcard $(sdir)/*.cu))
OBJ := $(patsubst %.cu,build/%.o,$(SRC))
INCLUDES := $(addprefix -I,headers)
# vpath %.cu $(SRC_DIR)
#define make-goal
build/%.o: %.cu
$(CC) $(INCLUDES) -c $< -o $#
#endef
.PHONY: all checkdirs clean
all: checkdirs build/lem
build/lem: $(OBJ)
$(LD) $^ -o $#
checkdirs: $(BUILD_DIR)
$(BUILD_DIR):
#mkdir -p $#
clean:
#rm -rf build
#$(foreach bdir,$(BUILD_DIR),$(eval $(call make-goal,$(bdir))))

Using GNU Make to build both debug and release targets at the same time (Extended)

I would like to follow up on this question and its answers... Now that I can build two different executables, I would like to build the executables in different directories, depending on a variable.
I would like to go from something like:
EXEDIR = bin/release/
EXE = $(EXEDIR)AmiModRadio
SOURCES = $(wildcard *.c)
OBJECTSDIR = o/release/
OBJECTS = $(addprefix $(OBJECTSDIR), $(SOURCES:.c=.o))
CC = vbcc:bin/vc
LD = vbcc:bin/vc
release : $(EXE)
$(OBJECTS) : $(OBJECTSDIR)%.o : %.c
$(CC) $(shell vbccprefs) -c $< -o $#
$(EXE) : $(OBJECTS)
$(LD) $(shell vbccprefs) -o $(EXE) $(OBJECTS)
to something like:
EXE = $(EXEDIR)AmiModRadio
SOURCES = $(wildcard *.c)
OBJECTS = $(addprefix $(OBJECTSDIR), $(SOURCES:.c=.o))
CC = vbcc:bin/vc
LD = vbcc:bin/vc
release : EXEDIR = bin/release/
release : OBJECTSDIR = o/release/
release : $(EXE)
release : EXEDIR = bin/debug/
release : OBJECTSDIR = o/debug/
release : $(EXE)
$(OBJECTS) : $(OBJECTSDIR)%.o : %.c
$(CC) $(shell vbccprefs) -c $< -o $#
$(EXE) : $(OBJECTS)
$(LD) $(shell vbccprefs) -o $(EXE) $(OBJECTS)
The last makefile above does not work because, as I understand it, setting the variables EXEDIR and OBJECTSDIR in the rules release and debug is too late.
So, am I missing something simple here? Is there a way to have the two rules release and debug use the same rules but generate the files in two different sets of directories, including the executables that are the main targets?
You can invoke the following Makefile as:
make release
make debug
-- OR --
make BUILD=release
make BUILD=debug
Makefile
ifneq ($(BUILD),release)
BUILD = debug
endif
EXEDIR = bin/$(BUILD)/
OBJDIR = o/$(BUILD)/
EXE = $(EXEDIR)AmiModRadio
SOURCES = $(wildcard *.c)
OBJECTS = $(addprefix $(OBJDIR), $(SOURCES:.c=.o))
CC = vbcc:bin/vc
LD = vbcc:bin/vc
CFLAGS = $(shell vbccprefs)
LDFLAGS = $(shell vbccprefs)
all : $(EXE)
.PHONY : release debug
release debug :
$(MAKE) BUILD=$#
$(EXE) : $(OBJECTS)
$(LD) $(LDFLAGS) -o $# $^
$(OBJDIR)%.o : %.c
$(CC) $(CFLAGS) -o $# -c $<
I would use a conditional to determine what the target is and set the variables accordingly.
ifeq "$(strip $(filter debug,$(MAKECMDGOALS)))" "debug"
EXEDIR = bin/release/
OBJECTSDIR = o/release/
endif
ifeq "$(strip $(filter release,$(MAKECMDGOALS)))" "release"
EXEDIR = bin/debug/
OBJECTSDIR = o/debug/
endif
The big issue that I see with your code is that you are specifying the release target on both the release and debug paths. So GNU Make uses the last assignment that it encounters. But, using what I have here should work as I do something similar with my make files.
In doing this, you cannot specify release and debug on the command line at the same time as they are mutually exclusive. The strip function strips out the leading and trailing whitespace from the parameter, which is the output of the filter function. The filter function takes the string debug and looks for it in the pre-defined variable MAKECMDGOALS. MAKECMDGOALS is a list of all the goals (targets) that was specified on the command line.
Hope this helps.

How can I create a Makefile for C projects with SRC, OBJ, and BIN subdirectories?

A few months ago, I came up with the following generic Makefile for school assignments:
# ------------------------------------------------
# Generic Makefile
#
# Author: yanick.rochon#gmail.com
# Date : 2010-11-05
#
# Changelog :
# 0.01 - first version
# ------------------------------------------------
# project name (generate executable with this name)
TARGET = projectname
CC = gcc -std=c99 -c
# compiling flags here
CFLAGS = -Wall -I.
LINKER = gcc -o
# linking flags here
LFLAGS = -Wall
SOURCES := $(wildcard *.c)
INCLUDES := $(wildcard *.h)
OBJECTS := $(SOURCES:.c=*.o)
rm = rm -f
$(TARGET): obj
#$(LINKER) $(TARGET) $(LFLAGS) $(OBJECTS)
#echo "Linking complete!"
obj: $(SOURCES) $(INCLUDES)
#$(CC) $(CFLAGS) $(SOURCES)
#echo "Compilation complete!"
clean:
#$(rm) $(TARGET) $(OBJECTS)
#echo "Cleanup complete!"
This will basically compile every .c and .h file to generate .o files and the executable projectname all in the same folder.
Now, I'd like to push this a little. How can I write a Makefile to compile a C project with the following directory structure?
./
./Makefile
./src/*.c;*.h
./obj/*.o
./bin/<executable>
In other words, I'd like to have a Makefile that compiles C sources from ./src/ into ./obj/ and then link everything to create the executable in ./bin/.
I've tried to read different Makefiles, but I simply can't make them work for the project structure above; instead, the project fails to compile with all sorts of errors. Sure, I could use full blown IDE (Monodevelop, Anjuta, etc.), but I honestly prefer to stick with gEdit and the good ol' terminal.
Is there a guru who can give me a working solution, or clear information about how this can be done? Thank you!
** UPDATE (v4) **
The final solution :
# ------------------------------------------------
# Generic Makefile
#
# Author: yanick.rochon#gmail.com
# Date : 2011-08-10
#
# Changelog :
# 2010-11-05 - first version
# 2011-08-10 - added structure : sources, objects, binaries
# thanks to http://stackoverflow.com/users/128940/beta
# 2017-04-24 - changed order of linker params
# ------------------------------------------------
# project name (generate executable with this name)
TARGET = projectname
CC = gcc
# compiling flags here
CFLAGS = -std=c99 -Wall -I.
LINKER = gcc
# linking flags here
LFLAGS = -Wall -I. -lm
# change these to proper directories where each file should be
SRCDIR = src
OBJDIR = obj
BINDIR = bin
SOURCES := $(wildcard $(SRCDIR)/*.c)
INCLUDES := $(wildcard $(SRCDIR)/*.h)
OBJECTS := $(SOURCES:$(SRCDIR)/%.c=$(OBJDIR)/%.o)
rm = rm -f
$(BINDIR)/$(TARGET): $(OBJECTS)
#$(LINKER) $(OBJECTS) $(LFLAGS) -o $#
#echo "Linking complete!"
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
#$(CC) $(CFLAGS) -c $< -o $#
#echo "Compiled "$<" successfully!"
.PHONY: clean
clean:
#$(rm) $(OBJECTS)
#echo "Cleanup complete!"
.PHONY: remove
remove: clean
#$(rm) $(BINDIR)/$(TARGET)
#echo "Executable removed!"
First, your $(OBJECTS) rule is problematic, because:
it's kind of indiscriminate, making all sources prerequisites of every object,
it often uses the wrong source (as you discovered with file1.o and file2.o)
it tries to build executables instead of stopping at objects, and
the name of the target (foo.o) is not what the rule will actually produce (obj/foo.o).
I suggest the following:
OBJECTS := $(SOURCES:$(SRCDIR)/%.c=$(OBJDIR)/%.o)
$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
$(CC) $(CFLAGS) -c $< -o $#
#echo "Compiled "$<" successfully!"
The $(TARGET) rule has the same problem that the target name does not actually describe what the rule builds. For that reason, if you type make several times, Make will rebuild the target each time, even though there is no reason to. A small change fixes that:
$(BINDIR)/$(TARGET): $(OBJECTS)
$(LINKER) $# $(LFLAGS) $(OBJECTS)
#echo "Linking complete!"
Once that's all in order, you might consider more sophisticated dependency handling; if you modify one of the header files, this makefile will not know which objects/executables must be rebuilt. But that can wait for another day.
EDIT:
Sorry, I omitted part of the $(OBJECTS) rule above; I've corrected it. (I wish I could use "strike" inside a code sample.)
You can add the -I flag to the compiler flags (CFLAGS) to indicate where the compiler should look for source files , and the -o flag to indicate where the binary should be left:
CFLAGS = -Wall -I./src
TARGETPATH = ./bin
$(TARGET): obj
#$(LINKER) $(TARGETPATH)/$(TARGET) $(LFLAGS) $(OBJECTS)
#echo "Linking complete!"
In order to drop the object files into the obj directory, use the -o option when compiling. Also, look at the $# and $< automatic variables.
For example, consider this simple Makefile
CFLAGS= -g -Wall -O3
OBJDIR= ./obj
SRCS=$(wildcard *.c)
OBJS=$(SRCS:.c=.o )
all:$(OBJS)
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $(OBJDIR)/$#
Update>
By looking at your makefile, I realize you are using the -o flag. Good. Continue using it, but add a target directory variable to indicate where the output file should be written.
I have stopped writing makefiles these days, if your intention is to learn go ahead, else you have good makefile generator that comes with eclipse CDT. If you want some maintainability / multiple project support with in your build tree, have a look at the following -
https://github.com/dmoulding/boilermake I found this pretty good..!

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