Trouble Writing My First Makefile - c

So here is my Makefile:
# My First Makefile
HEADERS = stdio.h
all: main.o input.o output.o
cc -o all main.o input.o output.o
main.o: main.c $(HEADERS)
cc -c main.c -o main.o
input.o: input.c $(HEADERS)
cc -c input.c -o input.o
output.o: output.c $(HEADERS)
cc -c output.c -o output.o
clean:
-rm -f *.o
-rm -f all
And below is input.c:
#ifndef __STDIO_H__
#define __STDIO_H__
#include <stdio.h>
void getChar()
{
getchar();
}
#endif
Below is output.c:
#ifndef __STDIO_H__
#define __STDIO_H__
#include <stdio.h>
void putChar(char c)
{
putchar(c);
}
#endif
Below is main.c:
#ifndef __STDIO_H__
#define __STDIO_H__
#include <stdio.h>
int main()
{
char c;
while ((c = etChar()) != '\n')
{
putChar(c);
}
}
#endif
Yet whenever I press "make" command in Terminal,
I get:
make: *** No rule to make target `stdio.h', needed by `main.o'. Stop.
cc refers to clang
What is it that I am doing wrong here?
I was trying to get used to $(ARGS) by using $(HEADERS)
but it seems that the clang compiler does not accept this.
Do you think I should use gcc instead?

It is unnecessary to write stdio.h in your Makefile. GCC will automatically search it in DEFAULT PATH (/usr/include, ....). Write header files as targes in Makefile only if you use your own header files.
# Makefile
# define CC
CC := gcc
# define final targets
TARGETS := main
# just trigger $(TARGETS)
all: $(TARGETS)
# build main from main.o, input.o, output.o
main: main.o input.o output.o
$(CC) -o $# $^
# build main.o/input.o/output.c from main.c/input.c/output.c
%.o: %.c
$(CC) -c -o $# $<
# trigger $(TARGETS), then run ./main
run: $(TARGETS)
./main
clean:
-rm $(TARGETS)
-rm *.o
# define targets which are not bound to file
.PHONY: all clean run

In your case:
"make" will look for stdio.h in the current directory, and is complaining that the header is not found.
Just to fix this, you should mention the full path where stdio.h is located, for example:
HEADERS = /usr/include/stdio.h
Ideally, if you want to check for the presence of standard headers like stdio.h, you should use tools like automake and autoconf, which generate the Makefile automatically. Here's a link which points to the autoconf documentation:
https://www.gnu.org/software/automake/manual/html_node/Autotools-Introduction.html

Related

Undefined reference to function that is already defined in my header file

I have three files, posl.h, state.c and main.c. What I plan on doing is adding functions that are used throughout the project in posl.h, and then I call it to test the function with main.c, and then make the function in state.c. The problem I am having is that I keep getting an error of undefined reference to init_poslState() even though I have it defined in posl.h
main.c
#include <posl.h>
int main(int argc, char * argv[]) {
pState poslState = init_poslState();
return 0;
}
posl.h
#ifndef POSL_LANGUAGE_H
#define POSL_LANGUAGE_H
#define POSL_MAJOR_VERSION 1
#define POSL_MINOR_VERSION 0
#define POSL_RELEASE_VERSION 0
// State
typedef struct POSL_STATE {
// ...
} pState;
pState init_poslState();
void free_poslState(pState poslState);
#endif
state.c
#include "state.h"
#include <posl.h>
pState init_poslState() {
pState newState;
return newState;
}
Makefile
CFLAGS=-g -Wall -Wextra -I./include
CC=gcc $(CFLAGS)
CORE_O_FILES=./src/Core/lexer.o ./src/Core/parser.o ./src/Core/state.o
CLI_O_FILES=
O_FILES=$(CORE_O_FILES)
# Making CLI Tool
posl: $(CLI_O_FILES) libposl.a ./src/CLI/main.c
$(CC) -o posl -L./ -lposl ./src/CLI/main.c $(CLI_O_FILES)
# Making Library
libposl.a: $(O_FILES) ./include/posl.h
ar rcs libposl.a $^
# Core Files
./src/Core/lexer.o: ./src/Core/lexer.c ./src/Core/lexer.h
$(CC) -o $# -c ./src/Core/lexer.c
./src/Core/parser.o: ./src/Core/parser.c ./src/Core/parser.h
$(CC) -o $# -c ./src/Core/parser.c
./src/Core/state.o: ./src/Core/state.c ./src/Core/state.h
$(CC) -o $# -c ./src/Core/state.c
# PHONY List
.PHONY: all
all:
make update-libs
make libposl.a
make posl
make pcc
# Post-Compile Clean
.PHONY: pcc
pcc:
rm -rf ./src/Core/*.o
rm -rf ./src/CLI/*.o
.PHONY: clean
clean:
make pcc
rm -rf ./libposl.a ./posl*
The order of compiler and (especially) linker options is significant. With this command ...
$(CC) -o posl -L./ -lposl ./src/CLI/main.c $(CLI_O_FILES)
... the linker will not attempt to resolve any function references from main.c against functions in libposl.a. It will look only to objects and libraries appearing after main.c on the command line.
Therefore, rewrite that recipe to
$(CC) -o posl -L. ./src/CLI/main.c $(CLI_O_FILES) -lposl
Welp, #user17732522 answered my question. I had the -l flag messed up, and it wasn't after my source files. ~Thank you guys!~

multiple definition of `function' error occurring on the same line as "first defined here"

error log
paging.c: In function ‘setup_paging_structures’:
paging.c:7: warning: implicit declaration of function ‘printf’
rm -f bootimg
gcc -nostdlib -static boot.o paging.o x86_desc.o i8259.o kernel.o lib.o paging.o tests.o -Ttext=0x400000 -o bootimg
paging.o: In function `setup_paging_structures':
/workdirmain/work/mp3_group_31/student-distrib/paging.c:4: multiple definition of `setup_paging_structures'
paging.o:/workdirmain/work/mp3_group_31/student-distrib/paging.c:4: first defined here
paging.o: In function `initialize_paging':
/workdirmain/work/mp3_group_31/student-distrib/paging.c:13: multiple definition of `initialize_paging'
paging.o:/workdirmain/work/mp3_group_31/student-distrib/paging.c:13: first defined here
collect2: ld returned 1 exit status
make: *** [bootimg] Error 1
Here's what my paging.h file looks like:
#ifndef _PAGING_H
#define _PAGING_H
#include "types.h"
#define TOTAL_ENTRIES 1024
extern void setup_paging_structures();
extern void initialize_paging();
#endif
Paging.c below:
#include "paging.h" //include header files
void setup_paging_structures(){
int i;
for (i = 0; i < TOTAL_ENTRIES; i++){
printf("weird");
}
return;
}
void initialize_paging(){
setup_paging_structures();
return;
}
Note, I have not called the functions yet.
The command I'm using is "sudo make" (Makefile was given to me. I'm pretty sure I'm not supposed to modify it):
# Makefile for OS project
# To build, first `make dep`, them `make`. Everything should be automatic.
# Will compile all *.c and *.S files in the current directory.
# Flags to use when compiling, preprocessing, assembling, and linking
CFLAGS+=-Wall -fno-builtin -fno-stack-protector -nostdlib
ASFLAGS+=
LDFLAGS+=-nostdlib -static
CC=gcc
#If you have any .h files in another directory, add -I<dir> to this line
CPPFLAGS+=-nostdinc -g
# This generates the list of source files
SRC=$(wildcard *.S) $(wildcard *.c) $(wildcard */*.S) $(wildcard */*.c)
# This generates the list of .o files. The order matters, boot.o must be first
OBJS=boot.o
OBJS+=$(filter-out boot.o,$(patsubst %.S,%.o,$(filter %.S,$(SRC))))
OBJS+=$(patsubst %.c,%.o,$(filter %.c,$(SRC)))
bootimg: Makefile $(OBJS)
rm -f bootimg
$(CC) $(LDFLAGS) $(OBJS) -Ttext=0x400000 -o bootimg
sudo ./debug.sh
dep: Makefile.dep
Makefile.dep: $(SRC)
$(CC) -MM $(CPPFLAGS) $(SRC) > $#
.PHONY: clean
clean:
rm -f *.o */*.o Makefile.dep
ifneq ($(MAKECMDGOALS),dep)
ifneq ($(MAKECMDGOALS),clean)
include Makefile.dep
endif
endif
edit: I added updates to my post including the actual directories, the entire error log, and the contents of the Makefile I am using. This is also for a class that I'm currently taking, hence some of the things that were automatically given to me.

`multiple definition of` lots of variables error - is my make file incorrect?

I am getting an error when I compile multiple definition of lots of variables. For example:
/tmp/ccwHwJ7t.o:(.data+0x0): multiple definition of `serial_number'
/tmp/ccmT1XNI.o:(.data+0x0): first defined here
All the variables are located in ftdi.h, which is included by main.c. Is there something wrong with my make file that is causing this to be included twice? or am I looking in the wrong directio.
SSHELL = /bin/sh
CC = gcc
APP = npi_usb_ftdi
INC = include
INCDIRS +=-I${INC}
CFLAGS= ${INCDIRS} -Wall -Wextra
LIBS = libftd2xx.a -ldl -lpthread -lrt
all: ${APP}
${APP}: src/main.c src/ftdi.c src/vt100.c src/monitor.c
${CC} ${CFLAGS} src/main.c src/ftdi.c src/vt100.c src/monitor.c -o ${APP} ${LIBS}
ftdi.o:
${CC} -c -o src/ftdi.o src/ftdi.c
vt100.o:
${CC} -c -o src/vt100.o src/vt100.c
monitor.o:
${CC} -c -o src/monitor.o src/monitor.c
clean:
rm -f src/*.o ; rm -f src/*~ ; rm -f *~ ; rm -f ${APP}
You probably include the .h file in other source files too. No problem, but only in one source file should the variables be declared and in the others just defined. I use:
// ftdi.h
#ifndef EXTERN
# define EXTERN extern
#endif
EXTERN int examplevar;
// main.c
#define EXTERN
#include "ftdi.h"
// ftdi.c
#include "ftdi.h"

Can't get my C program to compile. Makefile error

I am trying to create a new C program, but I can't get the program to compile. This is because my makefile seems to be wrong. I keep getting "No rule to make target 'all'" and "No rule to make target 'clean'". Here is what I have so far:
Main program:
#include <stdio.h>
Sleepy() {
main (); {
printf("Hello world");
}
}
Header (Although I haven't done anything to it yet):
#ifndef SLEEPY_H_
#define SLEEPY_H_
#endif /* SLEEPY_H_ */
And the Makefile:
CC = gcc
CFLAGS = -c
Sleepy.o: Sleepy.c Sleepy.h
$(CC) $(CFLAGS) Sleepy.c
Sleepy: Sleepy.o
$(CC) -o Sleepy.exe Sleepy.o
all: Sleepy
clean:
rm -rf *.0 a.out
make = all
I've been reading all kinds of tutorials, but I can't seem to get it to work. Would someone help me with this?
To achieve your compilation, following changes are required.
Sleepy.c
#include <stdio.h>
int main (void) {
printf("Hello world");
}
Makefile
CC = gcc
CFLAGS = -c
all: Sleepy
Sleepy.o: Sleepy.c Sleepy.h
$(CC) $(CFLAGS) Sleepy.c
Sleepy.exe: Sleepy.o
$(CC) -o Sleepy.exe Sleepy.o
clean:
rm -rf *.o Sleepy.exe
Please note the change in clean rule of your Makefile. You will have to remove the executable which is Sleepy.exe
NOTE: The rules for Sleepy.o and Sleepy should be offset by a TAB and not space. Else, you will run into this error: makefile:5: *** missing separator. Stop
try this one,
All: sleepy
sleepy: sleepy.c sleepy.o sleepy.h
gcc sleepy.c -o sleepy
clean:
rm -f *.o

Makefile Error : Command Not Found- while creating a shared library

I have 4 .c files hello.c,here.c,bye.c and main.c.
One header file mylib.h
The contents are as follows
hello.c
#include<stdio.h>
void hello()
{
printf("Hello!\n");
}
here.c
#include<stdio.h>
void here()
{
printf("I am here \n");
}
bye.c
#include<stdio.h>
void bye()
{
printf("Bye,Bye");
}
main.c
#include<stdio.h>
#include "mylib.h"
int main()
{
hello();
here();
bye();
return 1;
}
mylib.h
#ifndef _mylib_
#define _mylib_
void hello();
void here();
void bye();
#endif
The makefile for creating a static lib is :
Makefile
#Which Compiler
CC = gcc
#Compiler Flags
CFLAGS = - Wall -c -fPIC
DYNLINKFLAGS = -shared -W1,-soname,$#.0
PROG = main
PROG_OBJS = main.c
LIB = mylib
LIB_FILES = libmylib.so
LIB_MINOR = $(LIB_FILES).0.1
LIB_RELEASE = $(LIB_MINOR).0
LIB_OBJS = hello.o here.o bye.o
PATH = /home/srinivasa/cspp51081/labs/srinivasa.lab2.1
all: $(LIB_FILES) $(PROG)
#Create Lib with this file
$(LIB_FILES): $(LIB_OBJS)
$(CC) $(DYNLINKFLAGS) $^
ln -sf $(LIB_RELEASE) $(LIB_MINOR)
ln -sf $(LIB_MINOR) $#
ln -sf $# $#.0
#Compiling main program and link with shared library
$(PROG): $(PROG_OBJS)
$(CC) -o $(PROG) $(PORG_OBJS) -l$(LIB) -L$(PATH)
main.o: main.c
hello.o: hello.c
here.o: here.c
bye.o: bye.c
#clean files
clean:
rm -rf $(LIB_OBJS) $(LIB_FILES) $(LIB_RELEASE) $(LIB_MINOR) libmylib.so.0
Problem: When I execute the command
make -f Makefile all
I get the error:
gcc -Wall -fPIC -c -o hello.o hello.c
make: gcc: Command not found
make: * [hello.o] Error 127
Questions : How do I resolve this?
+++++
OK. Lets revert to your original code, but with a small difference.
Change DYNLINKFLAGS back to:
DYNLINKFLAGS = -shared -Wl,-soname,$#.0
Then change the library link to:
$(CC) $(DYNLINKFLAGS) -o $(LIB_RELEASE) $^
ln -sf $(LIB_RELEASE) $(LIB_MINOR)
ln -sf $(LIB_MINOR) $#
ln -sf $# $#.0
Do "rm -f lib*", build and then post make output.
There are a few bugs (just typos) I can see is:
space between - and Wall:
CFLAGS = - Wall -c -fPIC
^
PORG_OBJS should be PROG_OBJS
$(CC) -o $(PROG) $(PORG_OBJS) -L$(PATH)
^^^^
You are doing an absolute assignment to PATH. Now every executable called in makefile will be search in that directory. Since gcc is not found in that directory you get this error. To fix this you can either use a different variable name or add your directory to current path as:
PATH := $(PATH):/home/srinivasa/cspp51081/labs/srinivasa.lab2.1
^ ^^^^^^^^
Try changing this line from:
$(CC) -o $(PROG) $(PORG_OBJS) -l$(LIB) -L$(LIBPATH)
to:
$(CC) -o $(PROG) $(PORG_OBJS) -L$(LIBPATH) -l$(LIB)
The -L flag needs to precede the -l flags.
OK. First change:
DYNLINKFLAGS = -shared -W1,-soname,$#.0
to
DYNLINKFLAGS = -shared -W1,-soname,$#
Then change:
ln -sf $(LIB_RELEASE) $(LIB_MINOR)
ln -sf $(LIB_MINOR) $#
ln -sf $# $#.0
To:
ln -sf $# $(LIB_RELEASE)
ln -sf $# $(LIB_MINOR)
ln -sf $# $#.0
Then post the library links and the final executable link.

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