I’m currently working with an Arduino Due board which has an Atmel SAM3X8E processor embedded. I’m programming it using the Atmel Studio (version 7.0.1645) and the provided Atmel Software Framework (version 3.28.1).
The purpose of the program running on the SAM is to gain reprogramming functionality. Therefore the program gets the image from a host PC, flashes it block by block in the unused flash bank and verifies the image. All that is working fine, but I’m running into the same issue as this post (Atmel SAM3X dual bank switching not working).
The Atmel SAM3X8E has two 256-kByte flash banks, Flash0 and Flash1. My application easily fits in the Flash0 and is programming the received image to Flash1. My idea is to use the features of the SAM3X to boot from the other flash bank (default is Flash0). The datasheet of the SAM3X states at page 35 that GPNVM Bits can be used not only to choose the boot memory (ROM or Flash) but also to choose the bank to boot from (Flash0 or Flash1). If GPNVM2 is set the µC will boot from Flash1. This is achieved by remapping the memory layout. Therefore if GPNVM2 is set the Flash1 is mapped at address 0x0008_0000 (while Flash1 and Flash0 are continuous). If GPNVM2 is cleared Flash0 is mapped at address 0x0008_0000 (now Flash0 and Flash1 are continuous).
What I’ve done is to manipulate the GPNVM2 bit before resetting the processor, but it did not work (the memory was not remapped properly).
I was also playing around with the Atmel Studio’s options. Atmel Studio can program an application to Bank0 or Bank1 using the “Project Options” -> “Tool” -> “Program Settings”. I tried to program my application with these settings to Bank1. It is only possible if the checkbox “Override Vector Table Offset Register (exception_table)” is checked and if the device is programmed using “Start Debugging”. If the device is programmed using “Start without Debugging” it does not boot at all, to get it booting (remember the application was flashed to Bank1, if the remapping was successful Bank1 should be located at the address 0x0008_0000 where originally Bank0 is mapped to) I had to change the GPNVM bits manually (using the “Tools” -> “Device programming” Tool) to ‘boot from bank0’. Then it worked.
The described behaviour taught me that I must have missed to manipulate some registers. Obviously the “Override Vector Table Offset Register (exception_table)” is important therefore I also set the “Vector Offset Table Register (VTOR)” to the start address of Flash1 which didn’t help either. I’ve got the feeling I’m missing some functions or register that I have to call/manipulate.
To reprogram the processor it is normally necessary to have some kind of bootloader running which I hoped to avoid using the bank switching mechanics. Has anybody any experience about this bank switching using the ASF functions or in general about the bank switching on a SAM3X?
Thank you in advance!
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For a project I just started working on, I need to write a firmware in C that lets me boot into two different firmware versions. The task is to be able to update a device which includes an STM in the field using the RS485 Port with an Intel .hex file. My idea was to place the two firmware versions at designated starting addresses in the flash, including some kind of checksum for data integrity. According to the flash module organization found in the reference manual, my first thought was to place one version into sector 10 (starting at 0x080C0000) and the other version into sector 11 (starting at 0x080E0000). After every reset, the STM32 should boot into a "bootmanager" which is just minimum code that decides, whether the firmware in sector 10 or sector 11 is the newer version. I want to clarify my idea in the following graphic:
[Rough process][1]
[1]: https://i.stack.imgur.com/xLowh.png
The 128kBytes of every sector are sufficient. So far, I was able to write Single Bytes into the Flash and read them afterwards. Also, I have already set up a working UART communication using the RS485.
My questions
Can I just write the .hex file into the Flash as it is without modification like
:020000040800F2
:1000000002200B
etc?
As I am unexperienced with with jumps: How should I perform the jump from the "bootmanager" into sector 5 firmware? Are the adresses automatically relative to the entry point in sector 5?
Can you give me keywords or tell me, what challenges I will encounter?
*EDIT: I'm aware that the STM itself contains a bootloader. Unluckily, the RS485 device is hardwired to the GPIO pins used by USART2. According to the reference manual, the internal bootloader can only be used by USART1 and USART3, CAN2 and USB OTG FS
Can I just write the .hex file into the Flash as it is without
modification like
no you cant. You need to modify the linker script to archive it
You need to have the whole both applications in the FLASH so divide it 50/50%.
I usually add some serial FLASH to have a copy of the firmware if both of the images are damaged.
Yuo need to write the custom bootloader.
Most of the STM32 microcontrollers have support for dual memory bank and on the fly update (cf AN4767 - On-the-fly firmware update for dual bank STM32 microcontrollers)
This will allow to perform exactly what you require.
Usually the microcontroller will need to have a bootloader and 2 banks for the image.
When booting the bootloader will start and check which version it would have to boot and set the start address accordinngly.
This application note is for the F7 series but you can check it to see how it could work for your specific microcontroller (cf AN4826 - STM32F7 Series Flash memory dual bank mode).
Regarding your questions:
The code would be written as usual but twice (or 2 different firmwares)
Look into the application notes referenced and keywords such as: dual bank, on-the-fly update, DFU, etc
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How reboot procedure works on ARM SOCs running Linux, e.g do boot loaders reinitialize DDR memory? can anybody please explain me rebooting process in detail.
How reboot procedure works on ARM SOCs running Linux, ... ?
The typical ARM processor in use today is integrated with peripherals on a single IC called a SoC, system on a chip. Typically the reboot procedure is nearly identical to a power-on boot procedure. On a reset the ARM processor typically jumps to address 0.
Main memory, e.g. DRAM, and non-volatile storage, e.g. NAND flash, are typically external to the SoC (that is Linux capable) for maximum design flexibility.
But typically there is a small (perhaps 128KB) embedded ROM (read-only memory) to initialize the minimal system components (e.g. clocks, external memories) to begin bootstrap operations. A processor reset will cause execution of this boot ROM. (This ROM is truly read-only, and cannot be modified. The code is masked into the silicon during chip fabrication.)
The SoC may have a strapping option to instead execute an external boot memory, such as NOR flash or EEPROM, which can be directly executed (i.e. XIP, execute in place).
The salient characteristic of any ROM, flash, and SRAM that the first-stage boot program uses is that these memories must be accessible immediately after a reset.
One of the problems of bootstrapping a system that uses DRAM for main memory is its hardware initialization. The DRAM memory controller has to be initialized with board-specific parameters before code can be loaded into DRAM and executed. So from where does this board-specific initialization code execute, since it can't be in main memory?
Each vendor has their own solution.
Some require memory configuration data to be stored in nonvolatile memory for the boot ROM to access.
Some SoCs have integrated SRAM (which does not require initialization like DRAM) to execute a small second-stage bootstrap program.
Some SoCs use NOR flash to hold a XIP (execute in place) bootstrap program (e.g. the SPL program of U-Boot).
Each SoC vendor has its own bootstrap method to get the OS loaded and executing.
Some use hardware strapping read through GPIO pins to determine the source of the next stage of the bootstrap sequence.
Another vendor may use an ordered list of memories and devices to probe for a bootstrap program.
Another technique, is to branch to firmware in NOR flash, which can be directly executed (i.e. XIP, execute in place).
Once the bootstrap program has initialized the DRAM, then this main memory can be used to load the next stage of booting. That could be a sophisticated boot utility such as U-Boot, or (if the bootstrap program is capable) the Linux kernel. A ROM boot program could do everything to load an ARM Linux kernel (e.g. ETRAX), but more common is that there will be several bootstrap programs or stages that have be performed between processor reset to execution of the OS.
The requirements of booting the Linux ARM kernel are spelled out in the following document: Booting ARM Linux
Older versions of Linux ARM used the ATAGs list to pass basic configuration information to the kernel. Modern versions provide a complete board configuration using a compiled binary of a Device Tree.
... e.g do boot loaders reinitialize DDR memory?
Of the few examples that I have seen, the boot programs unconditionally configure the dynamic RAM controller.
PCs have a BIOS and Power On Self Tests, aka POST. The execution of POST is the primary difference between a power-on reset (aka cold boot) versus a software reset (aka warm boot or reboot). ARM systems typically do not perform POST, so you typically will see minimal to no difference between types of reset.
This is way too broad. It's not only SoC vendor dependent, but also hardware and software dependent.
However, the most typical setup is:
CPU executes first-stage bootloader (FSB).
FSB is located on the chip itself in ROM or EEPROM and is very small (AT91RM9200 FSB is 10kB max, AFAIR). FSB then initializes minimum set of peripherals (clocks, RAM, flash), transfers second-stage bootloader (U-Boot) to RAM, and executes it.
U-Boot starts.
U-Boot initializes some other hardware (serial, ethernet, etc), transfers Linux kernel to RAM, prepares the pointer to kernel input parameters and jumps into it's entry point.
Linux kernel starts.
Magic happens here. The system now able to serve you cookies via SSH console and/or executes whatever needs to be executed.
A bit more in-depth info about warm start:
Warm start is a software reset, while cold start is power-on or hardware reset. Some (most?) SoC's are able to pass the info to FSB/SSB about warm start. This way bootloaders are able to minimize the overall boot time by skipping re-initializion of already initialized peripherals.
Again, this is most typical setup from my 15+ years experience in embedded world.
It varies a lot depending on the SoC. I'll describe something like a "typical" one (Freescale iMX6)...
Typically an on-chip Watchdog Timer is used to reset the SoC cleanly. Sometimes, an external Power Management IC can be provoked to perform a board-wide reset (this method may be better, as it avoids the risk of external chips getting "stuck" in an unexpected state, but not all board designs support it).
Upon reset, the SoC will start its normal boot process: checking option pins, fuse settings and initializing clocks and the boot device (e.g. eMMC). This is typically controlled by CPU code executing from a small on-chip ROM.
Either the internal boot ROM will initialize DDR SDRAM (using settings taken from fuses or read from a file on the boot device), or the bootloader gets loaded into internal RAM then it takes care of DDR initialization (and other things). The U-Boot bootloader can be configured to work either way.
Finally, the kernel and DTB are loaded into memory and started.
note uboot, etc are not required they are GROSS overkill, they are operating systems in their own right. to load and run linux you need memory up and running copy the kernel branch to it with some registers set to point at tables that you setup or copied from flash along with the kernel.
What you do on a cold reset or warm is up to you, same chip and board no reason necessarily why any two solutions have to do the exact same thing unless it is driven by hardware (if you do a wdt reset to start over and that reset wipes out the whole chip including the ddr controller). You just have to put the system in the same state that linux expects.
The chip is an Energy Micro EFM32380f1024 ARM microcontroller and I am using IAR ARM Embedded Workbench. I am aware of the __ramfunc directive however accomplishing initialising and accessing USB completely in RAM (as the flash is going to be completely erased) requires all USB libraries that will be used to be placed in RAM?
This will be used to upgrade the firmware on the microcontroller hence the flash erase. The USB is initialised and used (for normal use by the firmware) for serial communications. I do not wish to use the bootloader for firmware upgrades.
as the flash is going to be completely erased
Not a good idea. In case the update process fails to write the new program completely and the power is lost, your device will be bricked.
Using a bootloader is strongly recommended when you want the flash to be updatable by a user.
I am currently working on firmware for a Stellaris ARM microcontroller board and I am running the SYS/BIOS RTOS.
I was wondering if the bootloader is required on the board when I upload my firmware onto it. Can I overwrite the bootloader on the flash with my .bin file, or am I required to offset my start address to preserve the bootloader.
In the general case (i.e. not specific to Stellaris), software is software, the bootloader is software, your application is software, the processor cannot tell the difference so quite evidently a bootloader is not required, the software that runs at reset could as easily be your software.
However the obvious benefit of a bootloader is the ability to apply in-field updates without connecting special equipment; you might regret loosing that capability.
Some chips (again generally, check your data sheet for Stelaris specifics) have a bootloader in mask ROM rather than Flash and you cannot delete or overwrite that, but usually configuration pins can be set to select the boot behaviour in order to by-pass the bootloader for example.
No you can use jtag and dont need running software in order to stop and re-flash the firmware.
I'm working on a custom Cortex-M3-based device and I need to implement in-application programming (IAP) mechanism so that it will be possible to update the device firmware without JTAG (we'll use TFTP or HTTP instead). While the IAP-related code examples available from ST Microelectronics are clear enough to me, I don't really understand how the re-flashing works.
As far as I understand, the instructions are fetched by the CPU from the Flash through the ICode bus (and the prefetch block, of course). So, here's my pretty silly question: why doesn't the running program get corrupted while it re-flashes itself (i.e. changes the Flash memory from which it is being run)?
A common solution is to have a small reserved area in the flash, where the actual flashing program is stored. When new firmware has been downloaded just make a jump to the code in this area.
Of course, this small area is not overwritten when flashing firmware, it can only be done by other means (like JTAG). So make sure this flashing-program works good to start with. :)
I'm not familiar with STM implementation, but in NXP chips the IAP routines are stored in a separate, reserved ROM area which can't be erased by user code.
If you're implementing the flash writing code yourself by using HW registers directly, you need to either make sure that it doesn't touch the sectors it's running from, or runs from the RAM.
Now a days many micro-controllers supporting IAP, that it is possible to program its flash memory while program execution in the same flash.
For IAP, program memory in the flash may be divided into 2 parts, one executable & other backup parts.
Generally we program the flash memory at a location (say, part-1) through JTAG, whose firmware version is 0.01. For IAP, i.e, program the flash in another part (part-2) while code is executing, corresponding API's should be provide in firmware version 0.01, which helps to program the flash part-2, After completion of programming successfully firmware version will be updated as 0.02. Upon processor restarts, program execution jumps to latest firmware by checking firmware version at initialization.
The part where the firmware is executing is called executable part, and other is back-up. why it is called back-up mean, suppose if there exists any firmware corruption while programming, firmware version will not update & upon restart, program control will automatically jumps back to back-up firmware after checking version number.
Another good way to do it is using custom made bootloader. However STM IAP is not stored in Flash so it can not be overwritten by it self. What generally people do is to spilt the flash in two parts , one is reserved for Custom made Bootloader and Another is for application. Bootloader makes sure that it does not write to its own assigned area. Bootloader can be programmed through JTAG and later application can utilize bootloader to program itself.
As far as I understand, the instructions are fetched by the CPU from the Flash through the ICode bus (and the prefetch block, of course). So, here's my pretty silly question: why doesn't the running program get corrupted while it re-flashes itself (i.e. changes the Flash memory from which it is being run)?
This is because, in general case writing/programming to flash memory is not allowed while you are reading from it(i.e executing code).
Have a look at this for some ideas on implementing IAP.