Can't store output of SystemVerilog module in 2D array - arrays

Question

I have a SystemVerilog module mFunc described as follows:
module mFunc #(parameter N = 1, parameter W=1)
(input logic signed [W:0] x[N],
output logic signed [W:0] Cx[N]);
always_comb
for(int k=0; k<N; k++)
Cx[k] = N-x[k];
endmodule: mFunc
and a module mFunc2 which calls mFunc:
module mFunc2 #(parameter N = 1, parameter W=1)
(input logic signed [W:0] x[N][N],
output logic signed [W:0] Cx[N][N]);
logic signed [W:0] x_rows[N];
logic signed [W:0] C_rows[N];
mFunc #(.N(N), .W(W)) mFunc_rows(.x(x_rows), .Cx(C_rows));
always_comb begin
for(int k=0; k<N; k++) begin
for(int j=0; j<N; j++)begin
x_rows[j] = x[k][j];
Cx[k][j] = C_rows[j];
end
end
end
endmodule: mFunc2
When I run simulation the behavior of the module is according to figure 1 and the output (C_rows) of mFunc is not stored properly in Cx, saving just the last value of C_rows as can be seen in Figure 1.
Please could anyone help me with this problem?
Figure 1: Statement of the problem
Here is the link of the simulation in EDA Playground
Thank you.

Answer 1

The reason you are seeing only the last row filling the entire matrix is due to how you've implemented the mFunc2 module. In it, you have combinational logic containing a for loop assigning Cx[k] to C_rows, which translates into x_rows being assigned to the x[N-1]. Then, the logic is in the mFunc module can convert that x_rows into C_rows for the x[N-1] row. Finally, your combinational logic in mFunc2 runs again, assigning all rows of Cx to that C_rows.
Thinking about it from a synthesis prospective, you are only ever instantiating a single mFunc module, which means the logic for translating a row from x to Cx only exists for a single row. As you have no clock or other synchronous mechanisms, you cannot feed a single row into the module and get its result, and then feed in the next row as you are trying to do with the for loop. To have the design work combinationally, you must create enough resources in the design to complete the task. In this case, that means having N (as there are N rows) mFunc modules, one for each row. Otherwise, you can introduce a clock and feed in a single row into mFunc every cycle for N cycles.
The purely combinational path is relatively easy, as all you need to do to your mFunc2 module is instantiate more mFunc in it. You can do this using a generate loop, or you can make use of array modules which work perfectly for your case:
module mFunc2 #(parameter N = 1, parameter W=1)
(input logic signed [W:0] x[N][N],
output logic signed [W:0] Cx[N][N]);
// Here, we make use of arrays of modules to make N instantiations of mFunc
// Note the [N] next to the mFunc_rows, meaning we are declaring an array
// of mFunc modules, ie N of them. These can be hooked up to the unpacked
// arrays x and Cx directly and will produce the desired output in Cx
mFunc #(.N(N), .W(W)) mFunc_rows[N](.x(x), .Cx(Cx));
endmodule: mFunc2
Quick side note, if you intend for W to be the bit width of the values in x and Cx, you need to declare them as logic signed [W-1:0] not logic signed [W:0] as the latter will produce variables of length W+1. Example, a byte would be [7:0], not [8:0] as it has 8 bits.