When I compile using my makefile I get these warnings:
clang: warning: -lllist: 'linker' input unused [-Wunused-command-line-argument]
clang: warning: argument unused during compilation: '-L./bin' [-Wunused-command-line-argument]
This is probably because I have messed something up in my Makefile (below). Am I not linking the lib properly? Can anyone point me toward the problem?
all: list parser
parser: list parserCal bin/LinkedListAPI.o bin/CalendarParser.o
ar cr bin/libcparser.a bin/LinkedListAPI.o bin/CalendarParser.o
list: listparser bin/LinkedListAPI.o
ar cr bin/libllist.a bin/LinkedListAPI.o
listparser: src/LinkedListAPI.c include/LinkedListAPI.h
gcc -Wall -std=c11 -c -Iinclude src/LinkedListAPI.c -o bin/LinkedListAPI.o
parserCal: src/CalendarParser.c include/LinkedListAPI.h include/CalendarParser.h include/HelperFunctions.h
gcc -Wall -std=c11 -c -L./bin -lllist -Iinclude src/CalendarParser.c -o bin/CalendarParser.o
TEST: list parser main.c
gcc -Wall -std=c11 -Iinclude main.c -o bin/runMe -L./bin -lllist -lcparser
clean:
rm bin/*.o bin/*.a
The immediate problem is in this rule:
TEST: list parser main.c
gcc -Wall -std=c11 -c -Iinclude main.c -o bin/runMe -L./bin -lllist -lcparser
The option -c means only compile, do not link, so any linker-related command line arguments are ignored, therefore you get that warning. Remove -c and it will work.
That said, this Makefile is "messed up". Normally, your targets should be the files created, e.g.
bin/libllist.a: listparser bin/LinkedListAPI.o
ar cr bin/libllist.a bin/LinkedListAPI.o
The way you do it, make is not more useful than a shell script, as it doesn't know which files are created and can't check whether rebuilding is necessary. Also, it would stop working at all if there was by accident a file named list. If you have rules that don't create a file, you must tell make about it by putting them as phony targets, e.g.:
.PHONY: all clean
a makefile is set of sequential things that need to be done, however, if a certain created file has no changes in its' dependency files, then that file will not be recreated.
It is best to be very specific about what specific utility program is to be run.
targets in the make file that don't actually create a file with the same name should be flagged using the .PSEUDO operator.
here is an example of a correctly written makefile, using the posted makefile as the basis: I've included a few comments in the makefile to clarify what is being done at each step
notice there (in this make file) is no mixing of compile parameters and rules with link parameters and rules
# use ':=' so the macro will only be evaluated once
# using just '=' results in the macro being reevaluated each time it is referenced.
# notice that desirable parameters are being set inside the macro definitions
CFLAGS := -Wall -Wextra -pedantic -std=c11
RM := /bin/rm -f
CC := /bin/gcc
AR := /bin/ar cr
# tell 'make' that these targets do not produce a file of the same name
.PSEUDO: all clean
# this is the first target in this makefile
# it lists the three 'final' targets
# so each of those target rules will be executed
all: bin/runMe bin/libcparser.a bin/libllist.a
# link step
bin/runMe: main.o bin/CalendarParser.o bin/LinkedListAPI.o
$(CC) main.o bin/CalendarParser.o bin/LinkedListAPI.o -o bin/runMe -L./bin -lllist -lcparser
# archive creation step
bin/libcparser.a: bin/LinkedListAPI.o bin/CalendarParser.o
$(AR) bin/libcparser.a bin/LinkedListAPI.o bin/CalendarParser.o
# archive creation step
bin/libllist.a: bin/LinkedListAPI.o
$(AR) bin/libllist.a bin/LinkedListAPI.o
# notice the archive targets and final runnable file
# reference certain dependencies.
# when a dependency is not available or not 'up to date'
# then the associated rule is executed to bring that dependency 'up to date'
# compile ./src/LinkedListAPI.c to create ./bin/LinkedListAPI.o
bin/LinkedListAPI.o: src/LinkedListAPI.c include/LinkedListAPI.h
$(CC) $(CFLAGS) -c src/LinkedListAPI.c -o bin/LinkedListAPI.o -Iinclude
# compile ./src/CalendarParser.c to create ./bin/calendarParser.o
bin/CalendarParser.o: src/CalendarParser.c include/LinkedListAPI.h include/CalendarParser.h include/HelperFunctions.h
$(CC) $(CFLAGS) -c src/CalendarParser.c -o ./bin/CalendarParser.o -Iinclude
# compile main.c to create main.o
main : main.c include/LinkedListAPI.h include/CalendarParser.h include/HelperFunctions.h
$(CC) $(CFLAGS) -c main.c -o main.o -Iinclude
clean:
$(RM) bin/*.o bin/*.a
Related
When trying to compile my c code I keep getting basic.c:5:10: fatal error: 'fftw3.h' file not found. I am compiling my c code using MacOS terminal and have Xcode installed.
I'm trying to write some c code which uses the fftw-3 library. fftw-3 has been installed using sudo port install fftw-3 and I have entered port contents fftw-3 which returned:
/opt/local/include/dfftw.h
/opt/local/include/dfftw_threads.h
/opt/local/include/drfftw.h
/opt/local/include/drfftw_threads.h
/opt/local/include/fftw_f77.i
/opt/local/lib/libdfftw.2.dylib
/opt/local/lib/libdfftw.a
/opt/local/lib/libdfftw.dylib
/opt/local/lib/libdfftw_threads.2.dylib
/opt/local/lib/libdfftw_threads.a
/opt/local/lib/libdfftw_threads.dylib
/opt/local/lib/libdrfftw.2.dylib
/opt/local/lib/libdrfftw.a
/opt/local/lib/libdrfftw.dylib
/opt/local/lib/libdrfftw_threads.2.dylib
/opt/local/lib/libdrfftw_threads.a
/opt/local/lib/libdrfftw_threads.dylib
/opt/local/share/info/fftw.info
/opt/local/share/info/fftw.info-1
/opt/local/share/info/fftw.info-2
/opt/local/share/info/fftw.info-3
/opt/local/share/info/fftw.info-4
/opt/local/share/info/fftw.info-5
I have been using a makefile and am trying to work out what needs including in it. At the moment I have:
# define the name of your source file(s)
SRCS = basic.c
# define the name of the object files(s) - we can do this automatically
OBJS = $(SRCS:.c=.o)
# tell MAKE which compiler to use
CCOMP = gcc
# flags for the compiler
# don't forget the -O3
CFLAGS = -Wall -O3 -fstrict-aliasing -Iinclude
#CFLAGS = -c -Wall -Iinclude
# flags for the linker. note -lm for the math library
LDFLAGS = -O3 -lm -L/opt/lib -I/opt/lib -L/opt/local/include -I/opt/lib
# the name of your executable file (the target) - here we put it in the top directory
TARGET = basic
# actions
all: $(OBJS)
$(CCOMP) -o $(TARGET) $(OBJS) $(LDFLAGS)
%.o: %.c
$(CCOMP) -c -o $# $< $(CFLAGS)
# delete all objects and target
clean:
rm -f $(OBJS) $(TARGET)
I'm not sure if the #CFLAGS and #LDFLAGS sections are correct? I would appreciate troubleshooting and any advice on what I need to do to get this working. Thanks!
I would like to know how the CFLAGS variable could be removed from the compilation and added when a parameter is given to the Makefile like "make cflags" without having to duplicate the compilation.
Here is a part of my Makefile :
EXE = $(PATH_EXE)/COLLECTEUR
all: ${EXE}
clean:
rm -f ${PATH_OBJ}/*.o
rm -f ${PATH_EXE}/*
clean_bin:
rm -f ${PATH_EXE}/*
link:
rm -f ${PATH_EXE}/*
$(PATH_EXE)/COLLECTEUR: $(PATH_OBJ)/Test.o $(OBJS)
${LD} ${CFLAGS} ${OBJS} $(PATH_OBJ)/Test.o ${LDFLAGS} -o $#
$(PATH_OBJ)/%.o : %.c
${CC} ${CFLAGS} $< -o $#
The general trick in make is to use a feature known as a target specific variable, which allows you to set or append to variables if a specific target is given, like so:
cflags: CFLAGS+=-Wall -Werror
cflags: all
What this says is for the target cflags append -Wall -Werror to the cflags, and the following line says that the cflags target depends on the all target.
Now, I did notice some errors in your compilation options.
The final link line ${LD} will invoke ld, which doesn't take ${CFLAGS} by default, you're probably better off using the compiler driver there as well (replace the ${LD} with ${CC}).
The compilation line for $(PATH_OBJ)/%.o files compiles and links the files, because it's missing the -c option, which instructs the compiler to compile only, and not to link.
[Files in my directory][1]
Need help compiling in a make file.
So I have this link list assignment i'm doing and the directions were.
stringlist.h is supposed to contain the node and the function prototypes
stringlist.c is supposed to have the functions completed that are defined in stringlist.h. BUT stringlist.c is not supposed to contain main at all. Then, namelist.c is supposed to contain main and just have the I/O and its just supposed to call the command functions that are in stringlist.c.
So to compile this we are supposed to create a make file. Whenever I try to I get an error because main doesn't exit in one of the c files. Throughout the term we compiled code like this "gcc -std=gnu99 -m32 -Wall -g -o file file.c"
But it doesn't work.
How would I create the make file? Been spending hours and can't figure it out.
As stated by Jonathan Leffler, the sample Makefile I provided had a few bad ideas. Here's an improvement:
# compiler:
CC = gcc
# compiler flags:
CFLAGS = -g -Wall
# the build target executable:
TARGET = executable
# object files to build:
OBJ = namelist.o stringlist.o
all: $(TARGET)
$(TARGET): $(OBJ)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJ)
Try this:
OBJ := namelist.c stringlist.c
GCC := gcc -g
CFLAGS := -std=gnu99 -m32 -Wall
compile: $(OBJ)
$(GCC) $(CFLAGS) $(OBJ) -o executable
When I do practice , I have a practice path.
Under this path , I have an Include path named myInclude (I have some useful function is this folder and I always use it.)
And a code path named symbol_try.I always make add new folder (with a c file and main function in it) in symbol_try and compile it.
Each time I have to compile it by gcc in terminal .Its a boring work , so I write a Makefile.
Here is an example:
the main Makefile in practice path:
FOBJS=
include myInclude/Rule.mk
include symbol_try/codeList_13.1/Rule.mk
symbol:$(FOBJS) <==What exactly I what . A executable file.
gcc -o symbol $(FOBJS) -pthread -lpthread
subsystem:
cd myInclude/ && $(MAKE)
cd symbol_try/codeList_13.1/ &&$(MAKE)
clean:
rm -rf symbol
In the myInclude/Rule.mk
FOBJS+=myInclude/otherFunction.o myInclude/error.o \
myInclude/unit.o myInclude/unitTest.o\
In the symbol_try/codeList_13.1/Rule.mk
FOBJS+=symbol_try/codeList_13.1/codeList_13.1.o
In myInclude/Makefile:
OBJS=otherFunction.o error.o unit.o unitTest.o
ALL:$(OBJS)
.PHONY:ALL
$(OBJS):%.o:%.c
gcc -c $< -o $#
clean :
otherFunction.o error.o unit.o
In symbol_try/codeList_13.1/Makefile:
codeList_13.1.o:codeList_13.1.c
gcc -c codeList_13.1.c
Well.That can work. But as you see , I have to write a Rule.mk(to initialize the FOBJS) and a Makefile for each folder.
I am new for make , I want find a way more concise , witch I only need write one Makefile for each folder and a main Makefile.No Rule.mk any more.
PS: I always change the code in myInclude ,so I don't want to build it a library.
Thanks for any help.
Here's one way you can do it with just one Makefile:
CC = gcc
CPPFLAGS += -I myInclude/ (1)
CFLAGS += -std=c99 -Wall (2)
VPATH = myInclude/ \ (3)
symbol_try/codeList_13.1/
symbol: otherFunction.o error.o unit.o unitTest.o codeList_13.1.o (4)
$(CC) -o $# $^ (5)
.PHONY : clean
clean:
rm -f symbol *.o
Note that make knows how to build C files and has some standard macros: CC, CPPFLGAS, CFLAGS
Add the include paths of your headers. You presumably have some headers for the individual object files in the myInclude directory.
Put the compiler flags here.
Add the paths to the source files you want to build.
List the object files that the executable depends upon
As there is no file called symbol.c you need to tell make how to create symbol.o with a rule. $# means the target ('symbol', here), and $^ means all of the prerequisites (the object files listed).
Here's a list of all of the files in my test directories for this:
$ find . -type f
.
./Makefile
./myInclude/error.c
./myInclude/header.h
./myInclude/otherFunction.c
./myInclude/unit.c
./myInclude/unitTest.c
./symbol_try/codeList_13.1/codeList_13.1.c
And the build output:
$ make
gcc -std=c99 -Wall -I myInclude/ -c -o otherFunction.o myInclude/otherFunction.c
gcc -std=c99 -Wall -I myInclude/ -c -o error.o myInclude/error.c
gcc -std=c99 -Wall -I myInclude/ -c -o unit.o myInclude/unit.c
gcc -std=c99 -Wall -I myInclude/ -c -o unitTest.o myInclude/unitTest.c
gcc -std=c99 -Wall -I myInclude/ -c -o codeList_13.1.o symbol_try/codeList_13.1/codeList_13.1.c
gcc -o symbol otherFunction.o error.o unit.o unitTest.o codeList_13.1.o
Why don't you create a library from the objects in myInclude and do the linking in the Makefile in your code path (symbol_try/codeList_13.1). The latter is better anyway because the needed libraries (-pthread -lpthread in your case) might change as well for some other code.
The main Makefile now would have got nothing to do but call make in all needed subdirectories.
In each folder have a makefile with
SOURCES=sample.c sampletest.c
OBJECTS=$(SOURCES:%.c=$(OBJDIR)/%.o)
all: $(OBJECTS)
$(OBJDIR)/%.o: %.c
$(CC) $(CFLAGS) -o $# $<
In the root directory of a project, create a makefile with a rule to compile every sub-folder like the below.
Dirs= path-to-rootdir
objs:
set -e ; \
for i in $(Dirs) ; do \
$(MAKE) CC="$(CC)" CFLAGS="$(CFLAGS_MODULE)" LDFLAGS="$(LDFLAGS)" OBJDIR="$(OBJDIR)" -C $$i; \
done
And then you could use it build the executable by adding a rule
EXE: objs
$(CC) -L./Path1 $(LIB_PATH) -llib1 -o $(EXE_NAME) $(wildcard $(OBJDIR)/*.o)
Hope this helps!!!
When we are compiling a C program the output is stored in a.out. How can we redirect the compiled output to another file?
Most C compilers provide an option for this, such as the -o option for gcc and some others:
gcc -o gentext gentext.c
cc -o mainprog -Llib -lmymath firstbit.c secondbit.o
xlc -o coredump coredump.c
-ofilename will make filename instead of a.out.
According to the manual:
-o <file> Place the output into <file>
In Unix, where C originated from, C programs are usually compiled module-by-module, and then the compiled modules are linked into an executable. For a project that consists of modules foo.c and bar.c, the commands would be like this:
cc -c foo.c
cc -c bar.c
cc -o myprog foo.o bar.o
(With -c, the output filename becomes the source file with the suffix replaced with .o.)
This allows you to also re-compile only those modules that have changed, which can be a big time saver for big programs, but can also become pretty tricky. (This part is usually automated using make.)
For a single-module program there's not really any point in first compiling to a .o file, and then linking, so a single command suffices:
cc -o foo foo.c
For single-module programs, it is customary to call the resulting executable program the same as the C source file without the .c suffix. For multi-module programs, there is no hard custom on whether the output is named after the file with the main function or not, so you're free to invent whatever strikes your fancy.
With the -o option.
gcc main.c -o myCoolExecutable.o
This is ok if your program consists of a single file. If you have more files I suggest using make: create a Makefile and then run the command make.
A Makefile is a file containing some rules for compilation.
An example can be the following (# means the line is a comment):
CXX = gcc
#CXXFLAGS = -std=c++11
#INC_PATH = ...
#LIBS = ...
SOURCEDIR := yourSourceFolder
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=$(SOURCEDIR)/obj
OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))
# ADD MORE WARNINGS!
WARNING := -Wall -Wextra
# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean
# The first rule is the default, ie. "make",
# "make all" and "make parking" mean the same
all: yourExecutableName
clean:
$(RM) $(OBJECTS) $(DEPENDS) yourExecutableName
# Linking the executable from the object files
# $^ # "src.c src.h" (all prerequisites)
yourExecutableName: $(OBJECTS)
$(CXX) $(WARNING) $^ -o $#
#$(CXX) $(WARNING) $(CXXFLAGS) $(INC_PATH) $^ -o $# $(LIBS)
-include $(DEPENDS)
$(OBJDIR):
mkdir -p $(OBJDIR)
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $< -o $#
Shortly CXX variable defines your compiler (gcc, g++), with CXXFLAGS you can define flags for your compilation (i.e. -std=c++11). Then you can include and define custom (INC_PATH and LIBS: not set in the example). With SOURCEDIR you can specify your source code directory (where *.c files are).Then SOURCES is basically telling that the source files for the compilation are all the files having extension *.c.
The Makefile contains a set of rules whose structure is the following:
output: inputs
commandToExecute
The rule to generate your executable file is
yourExecutableName: $(OBJECTS)
$(CXX) $(WARNING) $^ -o $#
which is equivalent to gcc -Wall -Wextra $(OBJECTS) -o yourExecutableName.
$(OBJECTS) are the object file resulting from the compilation. When the above rule is executed, if they are not found make will continue scanning the file to find a rule to generate them. In this case the rule to generate these files is:
$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
$(CXX) $(WARNING) -MMD -MP -c $< -o $#
If further information is needed let me know.
If foo will be your executable and bar.c is your source file then the command is:
gcc -o foo bar.c
Compile using:
cc -o <opfilename> <filename.c>
Execute using:
./<opfilename>
gcc filename.c -o outputfile
This command will directly create an outputfile.exe OR outputfile.out according to operating system. In place of filename.c OR outputfile we can enter path, as shown below.
gcc ./home/user/filename.c -o ./home/outputfile
The format of giving the Name of .exe file according to the User Choice in C Language
step 1 :- Run the gcc (or the compiler you have) in the below format on the Terminal
gcc -o put_your_name_you_want_to_give (space) your_file_name_you_want_to_execute
NB:- If you are Running "Vs Code" Use the 'Tab' key for the Auto completion.
step 2 :- Write down the name of the program in format
.\the_name_you_have_given.exe
you are done!
Assuming you are in ubuntu
step-1: run gcc with these commands to compile filename.c
gcc filename.c -o filename.out
filename.out will be created, (it might or might not be shown where the other files are stored)
step-2: execute the filename.out by
./filename.out
step-3: wait for the output
thats it , you are done