STM32F103C8T6 doesn't work after reset button - arm

Question

I have "Minimum System Development Board for ARM Microcontroller – STM32F103C8T6" with ST-LINK V2.
This is the main code followed by linker-script then startup:
1) main:
### Directives
.thumb # (same as saying '.code 16')
.syntax unified
.cpu cortex-m3
.fpu softvfp
.include "stm32f103.i"
.section .text
.org 0x00
.global main
.equ GPIOC_CRL ,GPIOC_BASE
.equ GPIOC_CRH ,GPIOC_BASE + 0x04
.equ GPIOC_ODR ,GPIOC_BASE + 0x0C
.equ RCC_APB2ENR ,RCC_BASE + 0x14
.equ LEDDELAY ,800000
main:
## Enable the Port C peripheral clock
ldr r6, = RCC_APB2ENR
mov r0, RCC_APB2ENR_IOPCEN
str r0, [r6]
## Set the config and mode bits for Port C bin 15 so it will
## be a push-pull output (up to 50 MHz)
## to '0011'.
ldr r6, = GPIOC_CRH
ldr r0, = 0x34444444
str r0, [r6]
## Load R2 and R3 with the "on" and "off" constants
mov r2, 0x8000 # value to turn on LED
mov r3, 0x0 # value to turn off LED
ldr r6, = GPIOC_ODR # point to Port C output data register
loop:
str r2, [r6] # clear Port C, pin 15, turning on LED
ldr r1, = LEDDELAY
delay1:
subs r1, 1
bne delay1
str r3, [r6] # set Port C, pin 15, turning off LED
ldr r1, = LEDDELAY
delay2:
subs r1, 1
bne delay2
b loop # continue forever
##st-flash write forth.bin 0x08000000
2) linker:
/*
*****************************************************************************
**
** File : LinkerScript.ld
**
** Abstract : Linker script for STM32F103C8Tx Device with
** 64KByte FLASH, 20KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
/* Entry Point */
ENTRY(Reset_Handler)
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
}
/* The size of the stack used by the application. NOTE: you need to adjust */
STACK_SIZE = 256;
/* The size of the heap used by the application. NOTE: you need to adjust */
HEAP_SIZE = 0;
SECTIONS
{
.isr_vector : { /* the vector table goes FIRST into FLASH */
KEEP(*(.isr_vector)) /* vector table */
. = ALIGN(4);
} >FLASH
.text : { /* code and constants */
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} >FLASH
.preinit_array : {
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array : {
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array : {
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array*))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
_etext = .; /* global symbols at end of code */
.stack : {
__stack_start__ = .;
. = . + STACK_SIZE;
. = ALIGN(4);
__stack_end__ = .;
} >RAM
.data : AT (_etext) {
__data_load = LOADADDR (.data);
__data_start = .;
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
__data_end__ = .;
_edata = __data_end__;
} >RAM
.bss : {
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = .;
} >RAM
PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );
PROVIDE ( __end__ = _ebss );
.heap : {
__heap_start__ = .;
. = . + HEAP_SIZE;
. = ALIGN(4);
__heap_end__ = .;
} >RAM
/* Remove information from the standard libraries
/DISCARD/ : {
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
/*.ARM.attributes 0 : { *(.ARM.attributes) }*/
}
3) startup:
/**
*************** (C) COPYRIGHT 2016 STMicroelectronics ************************
* #file startup_stm32f103xb.s
* #author MCD Application Team
* #version V4.1.0
* #date 29-April-2016
* #brief STM32F103xB Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global __stack_start__
.global __stack_end__
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word __data_load
/* start address for the .data section. defined in linker script */
.word __data_start
/* end address for the .data section. defined in linker script */
.word __data_end__
/* start address for the .bss section. defined in linker script */
.word __bss_start__
/* end address for the .bss section. defined in linker script */
.word __bss_end__
.equ BootRAM, 0xF108F85F
/**
* #brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* #param None
* #retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =__data_load
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =__data_start
ldr r3, =__data_end__
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =__bss_start__
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, =__bss_end__
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
/*bl SystemInit*/
/* Call static constructors */
/*bl __libc_init_array*/
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* #brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* #param None
* #retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word __stack_end__
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* #0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.align
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
When I try to flash this code with
st-flash write main.bin 0x08000000
I get the following :
st-flash 1.3.1
2017-07-03T21:42:39 INFO src/common.c: Loading device parameters....
2017-07-03T21:42:39 INFO src/common.c: Device connected is: F1 Medium-density device, id 0x20036410
2017-07-03T21:42:39 INFO src/common.c: SRAM size: 0x5000 bytes (20 KiB), Flash: 0x20000 bytes (128 KiB) in pages of 1024 bytes
2017-07-03T21:42:39 INFO src/common.c: Attempting to write 420 (0x1a4) bytes to stm32 address: 134217728 (0x8000000)
Flash page at addr: 0x08000000 erased
2017-07-03T21:42:40 INFO src/common.c: Finished erasing 1 pages of 1024 (0x400) bytes
2017-07-03T21:42:40 INFO src/common.c: Starting Flash write for VL/F0/F3 core id
2017-07-03T21:42:40 INFO src/flash_loader.c: Successfully loaded flash loader in sram
0/0 pages written
2017-07-03T21:42:40 INFO src/common.c: Starting verification of write complete
2017-07-03T21:42:40 INFO src/common.c: Flash written and verified! jolly good!
and the LED doesn't flash, but when I first upload any code using ARDUINO IDE(for this board) then I run the prevouis command, the led starts blinking, but if I pushed the reset button or unplug then plug st-link agian the LED stop blinking.
So I think the problem is with my linker or the startup code, but I don't know where it is.
What is wrong with startup code or linker script?
----- EDIT -----
result of disassembly:
arm-none-eabi-objdump -D main.elf > dump.S
main.elf: file format elf32-littlearm
Disassembly of section .isr_vector:
08000000 <g_pfnVectors>:
8000000: 20005000 andcs r5, r0, r0
8000004: 08000165 stmdaeq r0, {r0, r2, r5, r6, r8}
8000008: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
800000c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000010: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000014: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000018: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
...
800002c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000030: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000034: 00000000 andeq r0, r0, r0
8000038: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
800003c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000040: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000044: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000048: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
800004c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000050: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000054: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000058: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
800005c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000060: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000064: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000068: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
800006c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000070: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000074: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000078: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
800007c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000080: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000084: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000088: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
800008c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000090: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000094: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
8000098: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
800009c: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000a0: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000a4: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000a8: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000ac: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000b0: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000b4: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000b8: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000bc: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000c0: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000c4: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000c8: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000cc: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000d0: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000d4: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000d8: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000dc: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000e0: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000e4: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
80000e8: 080001a5 stmdaeq r0, {r0, r2, r5, r7, r8}
...
8000108: f108f85f ; <UNDEFINED> instruction: 0xf108f85f
Disassembly of section .text:
08000110 <main>:
8000110: 4e0a ldr r6, [pc, #40] ; (800013c <delay2+0x8>)
8000112: f04f 0010 mov.w r0, #16
8000116: 6030 str r0, [r6, #0]
8000118: 4e09 ldr r6, [pc, #36] ; (8000140 <delay2+0xc>)
800011a: 480a ldr r0, [pc, #40] ; (8000144 <delay2+0x10>)
800011c: 6030 str r0, [r6, #0]
800011e: f44f 4200 mov.w r2, #32768 ; 0x8000
8000122: f04f 0300 mov.w r3, #0
8000126: 4e08 ldr r6, [pc, #32] ; (8000148 <delay2+0x14>)
08000128 <loop>:
8000128: 6032 str r2, [r6, #0]
800012a: 4908 ldr r1, [pc, #32] ; (800014c <delay2+0x18>)
0800012c <delay1>:
800012c: 3901 subs r1, #1
800012e: d1fd bne.n 800012c <delay1>
8000130: 6033 str r3, [r6, #0]
8000132: 4906 ldr r1, [pc, #24] ; (800014c <delay2+0x18>)
08000134 <delay2>:
8000134: 3901 subs r1, #1
8000136: d1fd bne.n 8000134 <delay2>
8000138: e7f6 b.n 8000128 <loop>
800013a: bf00 nop
800013c: 40021014 andmi r1, r2, r4, lsl r0
8000140: 40011004 andmi r1, r1, r4
8000144: 34444444 strbcc r4, [r4], #-1092 ; 0xfffffbbc
8000148: 4001100c andmi r1, r1, ip
800014c: 000c3500 andeq r3, ip, r0, lsl #10
8000150: 080001a8 stmdaeq r0, {r3, r5, r7, r8}
8000154: 20005000 andcs r5, r0, r0
8000158: 20005000 andcs r5, r0, r0
800015c: 20005000 andcs r5, r0, r0
8000160: 20005000 andcs r5, r0, r0
08000164 <Reset_Handler>:
8000164: 2100 movs r1, #0
8000166: e003 b.n 8000170 <LoopCopyDataInit>
08000168 <CopyDataInit>:
8000168: 4b09 ldr r3, [pc, #36] ; (8000190 <LoopFillZerobss+0xc>)
800016a: 585b ldr r3, [r3, r1]
800016c: 5043 str r3, [r0, r1]
800016e: 3104 adds r1, #4
08000170 <LoopCopyDataInit>:
8000170: 4808 ldr r0, [pc, #32] ; (8000194 <LoopFillZerobss+0x10>)
8000172: 4b09 ldr r3, [pc, #36] ; (8000198 <LoopFillZerobss+0x14>)
8000174: 1842 adds r2, r0, r1
8000176: 429a cmp r2, r3
8000178: d3f6 bcc.n 8000168 <CopyDataInit>
800017a: 4a08 ldr r2, [pc, #32] ; (800019c <LoopFillZerobss+0x18>)
800017c: e002 b.n 8000184 <LoopFillZerobss>
0800017e <FillZerobss>:
800017e: 2300 movs r3, #0
8000180: f842 3b04 str.w r3, [r2], #4
08000184 <LoopFillZerobss>:
8000184: 4b06 ldr r3, [pc, #24] ; (80001a0 <LoopFillZerobss+0x1c>)
8000186: 429a cmp r2, r3
8000188: d3f9 bcc.n 800017e <FillZerobss>
800018a: f7ff ffc1 bl 8000110 <main>
800018e: 4770 bx lr
8000190: 080001a8 stmdaeq r0, {r3, r5, r7, r8}
8000194: 20005000 andcs r5, r0, r0
8000198: 20005000 andcs r5, r0, r0
800019c: 20005000 andcs r5, r0, r0
80001a0: 20005000 andcs r5, r0, r0
080001a4 <ADC1_2_IRQHandler>:
80001a4: e7fe b.n 80001a4 <ADC1_2_IRQHandler>
...
Disassembly of section .stack:
20000000 <__stack_start__>:
...
Disassembly of section .ARM.attributes:
00000000 <.ARM.attributes>:
0: 00002041 andeq r2, r0, r1, asr #32
4: 61656100 cmnvs r5, r0, lsl #2
8: 01006962 tsteq r0, r2, ror #18
c: 00000016 andeq r0, r0, r6, lsl r0
10: 726f4305 rsbvc r4, pc, #335544320 ; 0x14000000
14: 2d786574 cfldr64cs mvdx6, [r8, #-464]! ; 0xfffffe30
18: 0600334d streq r3, [r0], -sp, asr #6
1c: 094d070a stmdbeq sp, {r1, r3, r8, r9, sl}^
20: Address 0x0000000000000020 is out of bounds.

Answer 1

so.s
.thumb
.thumb_func
.global _start
_start:
stacktop: .word 0x20001000
.word reset
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.word hang
.thumb_func
reset:
b hang
.thumb_func
hang: b .
so.ld
MEMORY
{
rom : ORIGIN = 0x08000000, LENGTH = 0x1000
ram : ORIGIN = 0x20000000, LENGTH = 0x1000
}
SECTIONS
{
.text : { *(.text*) } > rom
.rodata : { *(.rodata*) } > rom
.bss : { *(.bss*) } > ram
}
commands
arm-none-eabi-as --warn --fatal-warnings -mcpu=cortex-m3 so.s -o so.o
arm-none-eabi-ld -o so.elf -T so.ld so.o
arm-none-eabi-objdump -D so.elf > so.list
arm-none-eabi-objcopy so.elf so.bin -O binary
so.list (partial)
Disassembly of section .text:
08000000 <_start>:
8000000: 20001000 andcs r1, r0, r0
8000004: 08000041 stmdaeq r0, {r0, r6}
8000008: 08000043 stmdaeq r0, {r0, r1, r6}
800000c: 08000043 stmdaeq r0, {r0, r1, r6}
8000010: 08000043 stmdaeq r0, {r0, r1, r6}
8000014: 08000043 stmdaeq r0, {r0, r1, r6}
8000018: 08000043 stmdaeq r0, {r0, r1, r6}
800001c: 08000043 stmdaeq r0, {r0, r1, r6}
8000020: 08000043 stmdaeq r0, {r0, r1, r6}
8000024: 08000043 stmdaeq r0, {r0, r1, r6}
8000028: 08000043 stmdaeq r0, {r0, r1, r6}
800002c: 08000043 stmdaeq r0, {r0, r1, r6}
8000030: 08000043 stmdaeq r0, {r0, r1, r6}
8000034: 08000043 stmdaeq r0, {r0, r1, r6}
8000038: 08000043 stmdaeq r0, {r0, r1, r6}
800003c: 08000043 stmdaeq r0, {r0, r1, r6}
08000040 <reset>:
8000040: e7ff b.n 8000042 <hang>
08000042 <hang>:
8000042: e7fe b.n 8000042 <hang>
with your linker script, added a label for Reset_Handler which doesnt do much since this is not being loaded from an operating system, but from flash (the vector table defines entry points not the elf, it isnt used in that form)
Disassembly of section .text:
08000000 <_start>:
8000000: 20001000 andcs r1, r0, r0
8000004: 08000041 stmdaeq r0, {r0, r6}
8000008: 08000043 stmdaeq r0, {r0, r1, r6}
800000c: 08000043 stmdaeq r0, {r0, r1, r6}
8000010: 08000043 stmdaeq r0, {r0, r1, r6}
8000014: 08000043 stmdaeq r0, {r0, r1, r6}
8000018: 08000043 stmdaeq r0, {r0, r1, r6}
800001c: 08000043 stmdaeq r0, {r0, r1, r6}
8000020: 08000043 stmdaeq r0, {r0, r1, r6}
8000024: 08000043 stmdaeq r0, {r0, r1, r6}
8000028: 08000043 stmdaeq r0, {r0, r1, r6}
800002c: 08000043 stmdaeq r0, {r0, r1, r6}
8000030: 08000043 stmdaeq r0, {r0, r1, r6}
8000034: 08000043 stmdaeq r0, {r0, r1, r6}
8000038: 08000043 stmdaeq r0, {r0, r1, r6}
800003c: 08000043 stmdaeq r0, {r0, r1, r6}
08000040 <reset>:
8000040: e7ff b.n 8000042 <hang>
08000042 <hang>:
8000042: e7fe b.n 8000042 <hang>
Then you can add more code to make it blink, I am not going to dig out an STM32F103 right now, could maybe cobble together something untested. will see.
Are you getting the 0x08000000 address with the vector table in the right place in your build seeing how to use the tools in this way?
from the way you dissassembled your file starts off okay
20000100
08000161
080001a1
080001a1
080001a1
080001a1
080001a1
that looks reasonable...I dont know if they are the correct addresses, but assume they are
this is working C code for the same chip but pin PC13 instead of 15.
void PUT32 ( unsigned int, unsigned int );
unsigned int GET32 ( unsigned int );
void dummy ( unsigned int );
#define GPIOCBASE 0x40011000
#define RCCBASE 0x40021000
int notmain ( void )
{
unsigned int ra;
unsigned int rx;
ra=GET32(RCCBASE+0x18);
ra|=1<<4; //enable port c
PUT32(RCCBASE+0x18,ra);
//config
ra=GET32(GPIOCBASE+0x04);
ra&=~(3<<20); //PC13
ra|=1<<20; //PC13
ra&=~(3<<22); //PC13
ra|=0<<22; //PC13
PUT32(GPIOCBASE+0x04,ra);
for(rx=0;;rx++)
{
PUT32(GPIOCBASE+0x10,1<<(13+0));
for(ra=0;ra<200000;ra++) dummy(ra);
PUT32(GPIOCBASE+0x10,1<<(13+16));
for(ra=0;ra<200000;ra++) dummy(ra);
}
return(0);
}
I am working through your disassembly to try to figure out what addresses you are using, they look wrong so far 0x40021014 instead of 0x40021018 to enable port c. (PUT32/GET32 are just store/load functions dummy just returns, used to prevent optimization)