Assigning 1 bit values to a multidimensional array in Verilog? - arrays

Question

I am writing a Verilog code in which a 1 bit input has to be serially assigned (bit-wise) to a 2D memory. As far as I understand if we make a memory then it can be assigned byte wise (or contiguously) only at run time. Is there any way I can easily fill up a multidimensional array bit wise in Verilog like in C. Here is a snippet of my code:
input in,clk;
reg [7:0] array [0:511];
reg [8:0] i=9'd 0;
reg [2:0] j=3'd 0;
always # (posedge clk)
begin
if (i<=9'd 511)
begin
if(j<=3'd 7)
begin
array[i][j]<=in;
j<=j+1;
end
else
j<=0;
i<=i+1;
end
else
i<=0;
end //end always
But this is not giving me the desired results in the post-route simulation. Any suggestions are welcome.

Answer 1

It is impossible for i & j to be above 511 & 7 respectively. Therefore, if (i<=9'd 511) and if(j<=3'd 7) will always evaluate to be true and the else condition is unreachable.
Furthermore your i<=i+1; does not have a condition statement so it will always incroment, updating the array in a diagonal: [0][0] -> [1][1] -> ... -> [7][7] -> [8][0] -> [9][1] -> .... I assume this is undesired.
To fill the byte before changing i, you should use something like this:
array[i][j] <= in;
if (j == 3'd7) begin
j <= 3'd0;
if (i == 9'd511) begin
i <= 0;
end
else begin
i <= i + 1;
end
end
else begin
j <= j + 1;
end
Since the addressable range is a power of two, you can simplify the logic
array[i][j] <= in;
j <= j + 1; // Reminder <= is eval now, update later
if (j == 3'd7) begin // 'j' here has the pre-eval value
i <= i + 1;
end
FYI: you should always run in simulation before post-route. It is way easier to debug RTL and a waveform.