I have the following makefile which is supposed to build procdriver.c and thus output a .ko file. The issue is that even when I delete procdriver.c my makefile seems to be able to build a procdriver.ko file. I would like to try to find out from where it gets the source file it is building every time.
TARGET = procdriver
obj-m := procdriver.o
procdriver-objs+= gpioLib.o
KDIR:= /home/pi/myRpi/linux
PWD := $(shell pwd)
all: gpioLib.o procdriver.c
echo<<"in all"
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
rm -r -f .tmp_versions *.mod.c .*.cmd *.o *.symvers
gpioLib.o: gpioLib.c gpioLib.h
gcc -c gpioLib.c -o gpioLib.o
clean:
make -C $(KDIR) SUBDIRS=$(PWD) clean
This is the output from the Makefile: http://paste.ubuntu.com/23575533/
EDIT
the entire output of the remake command: http://paste.ubuntu.com/23577274
I think this is the most important bit of output: http://pastebin.com/0vj9aNMg
obj-m := procdriver.o
procdriver-objs+= gpioLib.o
is wrong. It says that the sole object file for the module will be procdriver.o
and that the build system is to generate that one from procdriver-objs
procdriver-objs is initally empty and so becomes = gpioLib.o. So gpioLib.o
is the only object prerequisite of procdriver.o; hence gpioLib.c and gpioLib.h
are the only source prerequisites of procdriver.o. procdriver.c is redundant.
You want (I believe) to make a module from a pair of object files procdriver.o and gpioLib.o,
compiled respectively from the corresponding .c files. The way you need to express that is:
obj-m += my-module-name.o
my-module-name-objs := procdriver.o gpioLib.o
You will have to rethink your filenames to avoid a collision between my-module-name.o
and procdriver.o. Consult the documentation The Linux Kernel Module Programming Guide: 2.7. Modules Spanning Multiple Files.
Much of the content of your makefile is redundant. As far as I can see all it
needs is:
obj-m += my-module-name.o
my-module-name-objs := procdriver.o gpioLib.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
gpioLib.o: gpioLib.h
Related
Eg: a common device module's Makefile
obj-m:=jc.o
default:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules
clean:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules clean
I consider if I can set CFLAGS to the file. When I change default section to
$(MAKE) -O2 -C /lib/modules/$(shell uname -r)/build M=$(shell pwd) modules
But it didn't work.
Any help? Thanks a lot.
-O2 would be an option to make (or $(MAKE), as you're using it) in what you tried. Obviously, the compiler (probably gcc) needs this flag, not make.
Kbuild understands a make variable named CFLAGS_modulename.o to add specific C flags when compiling this unit. In your case, your module object will be jc.o, so you can specify:
CFLAGS_jc.o := -O2
and it should work. Add V=1 to your $(MAKE) lines to get a verbose output and you should see -O2 when jc.c is being compiled.
You can find more about compiling modules in the official documentation.
You can also use
ccflags-y := -O2
This will be applied to all of the source files compiled for your module with the Makefile. This is indirectly documented in the link provided by eepp in Section 4.2
I want to make multiple kernel modules by executing one Makefile.
I have following directories and files:
top level directory:
subdir0:
module0.c
Makefile
subdir1:
module1.c
Makefile
subdir2:
module2.c
Makefile
Makefile (I want to execute this)
I want to execute only the Makefile in the top level directory and all subdir Makefiles should be executed. I want to get one kernel module for each subdirectory.
This is my current setting but it does not work. If I execute make inside of a subdir, it builds the correct *.ko files. But if I execute the top level Makefile it just generates Module.symvers and modules.order and the output looks like every Makefile would be executed, but nothing is created inside of the subdirectories.
My top level Makefile has the following contents:
TARGETS := all clean
SUBDIRS := subdir0 subdir1 subdir2
.PHONY: $(TARGETS) $(SUBDIRS)
$(TARGETS): $(SUBDIRS)
$(SUBDIRS):
$(MAKE) -C $# $(MAKECMDGOALS)
My subdirectory Makefiles have the following code:
obj-m += module0.o
all:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
I would be glad if someone could help me.
Thanks,
micha
As #0andriy said, I had to use a Makefile similar to the subdirectory Makefiles. But instead of adding obj-m entries, I added all subdirectories to obj-y.
I want to write a Kernel Module and now I have written some files: a.c, b.c, b.h and d.h.
a.c includes b.h and d.h and b.h includes d.h too.
I wrote a Makefile like this:
ifneq ($(KERNELRELEASE),)
mymodule-objs :=a.c b.c
obj-m += a.o b.o
else
PWD := $(shell pwd)
KVER := $(shell uname -r)
KDIR := /lib/modules/$(KVER)/build
all:
rm -rf *.o *.mod.c *.symvers *order *.markers *.cmd *-
$(MAKE) -C $(KDIR) M=$(PWD)
clean:
rm -rf *.o *.mod.c *.symvers *order *.markers *.cmd *-
endif
But it doesn't work, how should I write a correct Makefile? I want to get a file name x.ko in end and.
After I use the 'make' command, and I use 'insmod' is give me a message:
insmod: ERROR: could not insert module a.ko: Unknown symbol in module
By the way I use Ubuntu 14.10. The kernel is 3.16.0-37-generic
obj-m += a.o b.o
will create two modules, a.ko and b.ko
if you want to create a single module out of both (which I suppose you do because of the line with mymodule-objs), replace that line with
obj-m += mymodule.o
mymodule.o will be built according to mymodule-objs and then turned into mymodule.ko using modpost.
And as said before, you're missing modules in your $(MAKE) line
Try modelling your Makefile after this?
https://unix.stackexchange.com/questions/122095/understanding-a-make-file-for-making-ko-files
You might not need mymodule-objs := a.c b.c. And I think you're missing modules after the $(MAKE) line
I am trying to compile my kernel module.
The .c file name is file1.c, but I need the .ko file name to be mod1.ko.
How can I do that?
My current makefile:
obj-m := mod1.o
KDIR :=/lib/modules/$(shell uname -r)/build
PDW := $(shell pwd)
all:
$(MAKE) -C $(KDIR) M=$(PDW) modules
clean:
$(MAKE) -C $(KDIR) M=$(PDW) clean
You should change your first line to something like this:
obj-m += module_name.o
module_name-y := file1.o
Where module_name is the module file name (in this example the output will be module_name.ko) and it will be build from file1.c. You can add more than one source file to the 2nd line, so it could be:
module_name-y := file1.o file2.o file3.o
In this case module_name.ko will be build from file1.c, file2.c and file3.c.
You should read this document if you want to fully understand Linux kernel makefiles. Your problem is described somewhere around line 190.
The solution looks like this:
obj-m += mod1.o
mod1-objs := file1.o
KBUILD_CPPFLAGS += -I$(PWD)/
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Is it possible to build a kernel module from several source files which one of them has the same name as the module?
For example:
I want to build "mymodule.ko" with the following source files:
mymodule.c
mymodule_func.c
This makefile doesn't work:
#Makefile
obj-m += mymodule.o
mymodule-objs := mymodule.o mymodule_func.o
thanks
I found a solution, I placed my source file in a sub folder:
Makefile
src/mymodule.c
src/mymodule_func.c
#Makefile
obj-m += mymodule.o
mymodule-objs := ./src/mymodule.o ./src/mymodule_func.o
all:
make -C $(KERNEL_PATH) M=$(PWD) modules
clean:
make -C $(KERNEL_PATH) M=$(PWD) clean
Proper way to fix in kernel make file would be as:
#
obj-m+= my_module.o
#append other source files except my_module.c which would be include by default
my_module-objs+= src1.o src2.o
As per my understanding it is not possible to have the module name and the source name to be the same. It would be better to provide module name as module.o and use the Makefile for compiling loadable kernel module as shown below,
Makefile
# If KERNELRELEASE is defined, we've been invoked from the
# kernel build system and can use its language.
ifneq ($(KERNELRELEASE),)
**obj-m := module.o
module-objs := mymodule.o mymodule_func.o**
# Otherwise we were called directly from the command
# line; invoke the kernel build system.
EXTRA_CFLAGS += -DDEBUG
else
KERNELDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
endif
clean:
$(MAKE) -C $(KERNELDIR) SUBDIRS=$(PWD) clean
You can use TARGET to name your .ko file as I did in this example:
TARGET = can
KDIR = /lib/modules/3.1.10-1.16-desktop/build
PWD := $(shell pwd)
obj-m += $(TARGET).o
can-objs := can_core.o can_open.o can_select.o can_sysctl.o can_write.o \
can_close.o can_ioctl.o can_read.o can_util.o \
can_debug.o can_error.o \
can_async.o can_sim.o
default:
make -C $(KDIR) M=$(PWD) modules
So after the build I ended with a bunch of object files and can.ko
Another solution is create symlink to the file, say:
mymodule.c: ln -sf mymodule.c _mymodule.c
Now, use _mymodule.o as the object name:
mymodule-objs := _mymodule.o
If anyone has stumbled upon this issue while working with Xilinx SoCs and petalinux, note the generated .bb (bitbake) file. Apart from specifying object files in the Makefile:
modulename-objs+= src1.o src2.o
all files (including headers) must be listed in the modulename.bb file's SRC_URI variable.