generalized aggregate in vhdl - arrays

Question

I have an array / vector and I want to generate a new array by processing the first. A simple example of what I need is that every i-th element from the new array is the sum of the i-1, i, and i+1 elements from the first one.
I know this can be done very easily in a sequential manner by iterating through the array. I was wandering if there any kind of assigning expression that would generalize this and make this a parallel operation.(like in math: new[i] := old[i - 1] + old[i] + old[i + 1], where i ∈ (1, n) ).

Answer 1

As your question is about parallelism, I assume that you are interested in the hardware that will be synthesized from your VHDL description, not by the simulation.
Parallelism is a matter of when all these additions take place? If your design is synchronous - let's say of the rising edge of a clock named clk - then:
subtype word: unsigned(7 downto 0);
type word_array is array(natural range <>) of word;
signal a: word_array(0 to 15);
signal b: word_array(1 to 14);
...
process(clk)
begin
if rising_edge(clk) then
for i in 1 to 14 loop
b(i) <= a(i - 1) + a(i) + a(i + 1);
end loop;
end if;
end process;
will compute in parallel the 14 values in array b at each rising edge of the clock. And it will instantiate as many 8-bits adders as needed to do this. The question is not whether you are using a for loop or something else, it is really when do these operations take place? The answer is in the description: during the very same clock period.
You could overload the "+" operator to work on vectors:
function "+"(a, b: word_array) return word_array is
constant n: positive := a'length;
variable va: word_array(0 to n - 1) := a;
variable vb: word_array(0 to n - 1) := b;
variable sum: word_array(0 to n - 1);
begin
if n = 1 then
sum(0) := va(0) + vb(0);
else
sum := (va(0 to n / 2 - 1) + vb(0 to n / 2 - 1)) &
(va(n / 2 to n - 1) + vb(n / 2 to n - 1));
end if;
return sum;
end function "+";
and use it to apparently write a more parallel description:
process(clk)
begin
if rising_edge(clk) then
b <= a(0 to 13) + a(1 to 14) + a(2 to 15);
end if;
end process;
but it would make no difference and the resulting hardware would be the same.
You could also use a generate statement to do the same:
g: for i in 1 to 14 generate
process(clk)
begin
if rising_edge(clk) then
b(i) <= a(i - 1) + a(i) + a(i + 1);
end if;
end process;
end generate g;
but, again, it would make no difference for the synthesizer.