How bitwise shift operator is Implemented in C. Is it atomic? - c

Question

I want to know how bitwise shift operator "<<" and ">>" is implemented in language. Is it atomic or not? Does c shift the whole word at once or move every bit one by one.
Are there any dependencies on the compiler, operating system or computer architecture?
Does C standard defines how shift operator would be implemented?
Example :
let's say two thread are accessing a data. one of them modifies it by shifting 3 bits. so does this 3 bit shift an atomic operation or not? should I use locks to handle this modification?
EDIT: It's only a shift operator, no store instruction. data is already in memory so no load operation.
My processor : Powerpc MPC8569, e600 core architecture.

Answer 1

C only guarantees atomic access for _Atomic type variables, which were introduced in C11.
For all other situations, there are never any guarantees of atomic access. You will have to disassemble to C code to see how many assembler instructions it generated. Typically, one assembler instruction is always atomic.
But your question doesn't make all that much sense, because there is no context. Where would the result of the shift go? Do you plan to store it somewhere? Then that's two operations: shift and store. Possibly also a load. If you write an algorithm which is not atomic in itself, how do you expect the compiler to magically make it atomic for you?

Answer 2

It depends on the processor that you are using.
If an instruction for bitwise shift is present, as is present on most x86 cores and 16 bit and 32 bit microcontrollers, then it is atomic.
If, however you have a 8 bit microcontroller without a bit shift instruction, or you are trying to bit shift a large value (say 64 bits or 128 bits) the instruction may well take quite a lot of code.

Answer 3

It depends upon which standard you are talking about.
AFAIU, the only atomic operations (explicitly defined as atomic) in C11 are the ones related to <stdatomic.h>
You could imagine a TeraHertz processor with a 4 bits ALU; even a simple int32_t addition won't be atomic on it.

Answer 4

I wrote two program
#include<stdio.h>
int main()
{
int i = 5;
return 0;
}
Its assembly code generated for PowerPC architecture Code 1 is
.file "hello.c"
.section ".text"
.align 2
.globl main
.type main, #function
main:
stwu 1,-32(1)
stw 31,28(1)
mr 31,1
li 0,5
stw 0,8(31)
li 0,0
mr 3,0
lwz 11,0(1)
lwz 31,-4(11)
mr 1,11
blr
.size main, .-main
.ident "GCC: (GNU) 4.2.2"
.section .note.GNU-stack,"",#progbits
Second code is
#include<stdio.h>
int main()
{
int i = 5;
i = i<<1;
return 0;
}
My assembly code generated for PowerPC architecture code 2 is
.file "hello.c"
.section ".text"
.align 2
.globl main
.type main, #function
main:
stwu 1,-32(1)
stw 31,28(1)
mr 31,1
li 0,5
stw 0,8(31)
lwz 0,8(31) // extra
slwi 0,0,1 // extra
stw 0,8(31) // extra
li 0,0
mr 3,0
lwz 11,0(1)
lwz 31,-4(11)
mr 1,11
blr
.size main, .-main
.ident "GCC: (GNU) 4.2.2"
.section .note.GNU-stack,"",#progbits
You see there are three extra Instruction, So operation is not atomic
I also compiled this on Intel i7 PC. Here are the results:
assembly code generated for first code is :
.file "hello.c"
.text
.globl main
.type main, #function
main:
.LFB0:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movl $5, -4(%rbp)
movl $0, %eax
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE0:
.size main, .-main
.ident "GCC: (Ubuntu 4.8.4-2ubuntu1~14.04.1) 4.8.4"
.section .note.GNU-stack,"",#progbits
Assembly code generated for code 2:
.file "hello.c"
.text
.globl main
.type main, #function
main:
.LFB0:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
movl $5, -4(%rbp)
sall -4(%rbp) // only one extra instruction
movl $0, %eax
popq %rbp
.cfi_def_cfa 7, 8
ret
.cfi_endproc
.LFE0:
.size main, .-main
.ident "GCC: (Ubuntu 4.8.4-2ubuntu1~14.04.1) 4.8.4"
.section .note.GNU-stack,"",#progbits
So, my understanding is that, answer depends on architecture we are using.

Answer 5

Normally it should be SHLD/SHRD - Double Precision Shift (386+)
https://web.itu.edu.tr/kesgin/mul06/intel/instr/shld_shrd.html
I think it's atomic because it's a single instruction. Otherwise you could use atomic or volatile if c supports it, C++11 supports it.