This is a makefile that fails to link the .o files to make an executeable.
enter code here
CC = c99
CFLAGS = -g -Wall -Wextra -O0
OBJECTS = main.o getoptions.o
P = testprog
$(P): $(OBJECTS)
$(CC) $(OBJECTS) -o $(P)
main.o : main.c
$(CC) $(CFLAGS) $(OBJECTS) -c main.c
getoptions.o : getoptions.c getoptions.h
$(CC) $(CFLAGS) -c getoptions.o
I get this warning:
gcc: warning: getoptions.o: linker input file unused because linking not done
When I manually use:
c99 *.o -o testprog
linking succeeds.
Two issues here:
First, in your target for getoptions.o, you're passing getoptions.o for the -c option. You should be giving it the value of the source file getoptions.c
Second, get rid of $(OBJECTS) in the target for main.o. You don't need to pass in the object files for this step.
With those fixes you'll get a successful compilation:
c99 -g -Wall -Wextra -O0 -c main.c
c99 -g -Wall -Wextra -O0 -c getoptions.c
c99 main.o getoptions.o -o testprog
Edit:
The target line for main.o should be:
main.o : main.c getoptions.h
That way, if getoptions.h changes, main.o gets rebuilt.
Related
WHAT I NEED TO DO
I'm trying to create a Makefile in c that should create three executable from three different .c files.
I'll want to create Lez4Es1, Lez4Es1v2 and Lez4Es3 as my executable compiling and linking in two different stages.
Something as:
gcc -std=c99 -Wall -pedantic Lez4Es1.c -c
gcc -std=c99 -Wall -pedantic Lez4Es1.o -o Lez4Es1
gcc -std=c99 -Wall -pedantic Lez4Es1v2.c -c
gcc -std=c99 -Wall -pedantic Lez4Es1.v2 -o Lez4Es1v2
gcc -std=c99 -Wall -pedantic Lez4Es3.c -c
gcc -std=c99 -Wall -pedantic Lez4Es3.o -o Lez4Es3
MY SOLUTION
Assuming to have all .c files in the same directory i created this Makefile but it does not work:
CC = gcc
CFLAGS += -std=c99 -Wall -pedantic -g
TARGETS = Lez4Es1 \
Lez4Es1v2 \
Lez4Es3 \
.PHONY: all clean cleanall
% : %.o
$(CC) $(CFLAGS) $^ -o $#
%.o : %.c
$(CC) $(CFLAGS) -c $^
all : $(TARGETS)
clean :
-rm *.o *~ core
cleanall :
-rm *.o *.txt -f $(TARGETS) *~ core
PROBLEMS
When i run $ make it creates executable from .c file and not from .o, this is output of compiler:
$ make
gcc -std=c99 -Wall -pedantic -g Lez4Es1.c -o Lez4Es1
gcc -std=c99 -Wall -pedantic -g Lez4Es1v2.c -o Lez4Es1v2
gcc -std=c99 -Wall -pedantic -g Lez4Es3.c -o Lez4Es3
How to fix to let him do the things i want to do?
There is a method to give executable files a different name than .o files?
Sorry for my bad english and if i didn't explain it well i'm ready to edit it and give you more details, thank you.
Try deleting the built-in rule that creates executables from source files:
% : %.c
(a pattern rule with no recipe cancels that rule).
When I compile my code on the command line, there are no problems:
$ gcc -Wall -O2 -o mess main.c getmatrix.c toktoint.c prtmatrix.c getdist.c
But when I compile via make, it fails:
$ make clean
$ make
/usr/bin/gcc -O2 -Wall -c toktoint.c -o toktoint.o
/usr/bin/gcc -O2 -Wall -c getmatrix.c -o getmatrix.o
/usr/bin/gcc -O2 -Wall -c prtmatrix.c -o prtmatrix.o
/usr/bin/gcc -O2 -Wall -c getdist.c -o getdist.o
/usr/bin/gcc -O2 -Wall -c -o main.o main.c
/usr/bin/gcc -O2 -Wall -o mess toktoint.o
/usr/lib/gcc/x86_64-pc-cygwin/10/../../../../x86_64-pc-cygwin/bin/ld: /usr/lib/gcc/x86_64-pc-cygwin/10/../../../../lib/libcygwin.a(libcmain.o): in function `main':
/usr/src/debug/cygwin-3.1.7-1/winsup/cygwin/lib/libcmain.c:37: undefined reference to `WinMain'
/usr/src/debug/cygwin-3.1.7-1/winsup/cygwin/lib/libcmain.c:37:(.text.startup+0x82): relocation truncated to fit: R_X86_64_PC32 against undefined symbol `WinMain'
collect2: error: ld returned 1 exit status
make: *** [Makefile:44: mess] Error 1
Here is my Makefile:
CC=/usr/bin/gcc
OPTIMIZATION=2
CFLAGS=-O$(OPTIMIZATION) -Wall
LFLAGS=
TARGET=mess
OBJECTS=toktoint.o \
getmatrix.o \
prtmatrix.o \
getdist.o \
main.o
SOURCES=toktoint.c \
getmatrix.c \
prtmatrix.c \
getdist.c \
main.c
HEADERS=getmatrix.h \
toktoint.h \
prtmatrix.h \
getdist.h
all: $(TARGET)
mess: $(OBJECTS)
$(CC) $(CFLAGS) -o $# $<
%.o: %.c %.h
$(CC) $(CFLAGS) -c $< -o $#
clean:
#rm -f $(OBJECTS) $(TARGET)
I tried changing various flags, such as "-m64". And other suggestions which I found on stackoverflow, but no success.
If I compile each module on the command line, it also works:
$ make clean
$ gcc -O2 -Wall -c toktoint.c -o toktoint.o
$ gcc -O2 -Wall -c getmatrix.c -o getmatrix.o
$ gcc -O2 -Wall -c prtmatrix.c -o prtmatrix.o
$ gcc -O2 -Wall -c getdist.c -o getdist.o
$ gcc -O2 -Wall -c main.c -o main.o
$ gcc -Wall -O2 -o mess main.o getdist.o getmatrix.o prtmatrix.o toktoint.o
So it appears the problem is with make or Makefile.
Look at the output from make again, especially the linker line:
/usr/bin/gcc -O2 -Wall -o mess toktoint.o
It does not build with all the object files. Most notably, it misses main.o which I assume contains your main function.
The variable $< is only
The name of the first prerequisite
(from this make manual, emphasis mine).
To get all prerequisites (all object files) use $^:
mess: $(OBJECTS)
$(CC) $(CFLAGS) -o $# $^
I'm learning how to use C and Make, but Make is making me tear my hair out. When I run make with all targets I've created it fails, running gcc with no parameters, except one of them randomly works just fine. Here is what happens when I try to build with most of the targets:
$ make strvector.o
gcc
gcc: fatal error: no input files
compilation terminated.
make: *** [vector.o] Error 4
and when I run the one that works:
$ make word.o
gcc -Wall -g -ansi -pedantic -c -o word.o word.c
Here is my makefile:
CC = gcc
CFLAGS = -Wall -g -ansi -pedantic -c -o $# $^
LD = gcc
LDFLAGS =
fw: fw.o vector.o hashtable.o strvector.o
$(LD) $(LDFLAGS) -o fw vector.o hashtable.o strvector.o word.o
fw.o: fw.c vector.o hashtable.o strvector.o word.o
$(CC) $(CFALGS)
vector.o: vector.c word.o
$(CC) $(CFALGS)
hashtable.o: hashtable.c vector.o word.o
$(CC) $(CFLAGS)
word.o: word.c
$(CC) $(CFLAGS)
strvector.o: strvector.c
$(CC) $(CFALGS)
I cannot for the life of me figure out why word.o builds fine but not anything else. If anyone could help that would be much appreciated.
--Edit-- I made a typo. Writing CFALGS instead of CFLAGS. not sure how I missed that one. Thanks guys!
You left out the filenames in the compilation commands.
strvector.o: strvector.c
$(CC) -c $(CFLAGS) -o $# $<
$# gets replaced with the current target, $< is replaced with the current dependency.
How can I get a makefile of my C program that will build/compile my program and generates an
executable.This executive should be able to run my c program???
Save the makefile as makefile or Makefile:
.PHONY: all
all : progname
progname: all-objects
.PHONY to mark the target all as not a file-target
all is the first and thus default-target, depends on progname (Just so make all works)
progname depends on all the object-files, and will thus link them together.
The object-files are built using builtin rules.
If you want to override the default-action of a rule, write your own recipe.
Each command-line must be indented one tab (do not use spaces).
Reference of GNU make: http://www.gnu.org/software/make/manual/make.html
Reference of builtin rules: https://www.gnu.org/software/make/manual/html_node/Catalogue-of-Rules.html
Create a file called Makefile on the same path with this content:
CC = gcc
CFLAGS = -std=c99 -pedantic -Wall
OBJECTS = filename.o
all: appname
filename.o: filename.c
$(CC) $(CFLAGS) -c filename.c
appname: $(OBJECTS)
$(CC) $(OBJECTS) -o appname
Note: There must be a "tab" (not spaces) before
$(CC) $(CFLAGS) -c filename.c
and
$(CC) $(OBJECTS) -o appname
Then run:
make
EDIT: An example:
david#debian:~$ cat demo.c
#include <stdio.h>
int main(void)
{
return 0;
}
david#debian:~$ cat Makefile
CC = gcc
CFLAGS = -std=c99 -pedantic -Wall
OBJECTS = demo.o
all: demo
demo.o: demo.c
$(CC) $(CFLAGS) -c demo.c
demo: $(OBJECTS)
$(CC) $(OBJECTS) -o demo
david#debian:~$ make
gcc -std=c99 -pedantic -Wall -c demo.c
gcc demo.o -o demo
I have a make file that I am trying to a make more flexible. So, if I am building an executable, there is primary.c and primary.h. Along with that, there are two other pairs of files that I need to build into the executable: helper_funcs.c / helper_funcs.h and fork.c / fork.h.
CC = gcc
CFLAGS = -c -g -Wall -Wextra
SOURCES = fork.c helper_funcs.c
DEPS = primary.h fork.h helper_funcs.h
OBJECTS = $(SOURCES:.c=.o)
EXECUTABLE = primary
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(OBJECTS) -o $#
.c.o: $(DEPS)
$(CC) $(CFLAGS) $< -o $#
clean:
rm -f *.o
rm -f $(EXECUTABLE)
My goal is to write this make file such that no matter how many additional source files I may have, all I have to do is add them to the SOURCES list and the Makefile will handle the compilation and linking.
When I go to compile this, I get the following:
rm -f *.o
rm -f primary
gcc -c -o fork.o fork.c -c -g -Wall -Wextra
gcc -c -o helper_funcs.o helper_funcs.c -c -g -Wall -Wextra
gcc -c -o primary.o primary.c -c -g -Wall -Wextra
primary.c: In function ‘build_state’:
primary.c:114: warning: implicit declaration of function ‘make_passive’
primary.c:120: warning: implicit declaration of function ‘make_active’
primary.c:127: warning: implicit declaration of function ‘string_builder’
primary.c: In function ‘main’:
primary.c:172: warning: implicit declaration of function ‘read_file’
gcc fork.o helper_funcs.o routed_LS.o -o routed_LS
The functions that it doesn't see are those included in the helper_funcs.c file. It seems to be picking up the functions in fork.c, but I can't understand where the difference lies.
Can anyone help me figure out how to clear these errors? Thanks!