I was walking through this tutorial, where I had to create this make file:
CFLAGS=-wall -g
clean:
rm -f ex1
When I type this command:
$ make clean
I get the following error:
make: *** No rule to make target `clean'. Stop.
I made sure that I'm using TABS. Why am I getting this error? How can I solve it?
The issue here, as indicated by a few comments on the post is that you named your file make instead of the traditional Makefile (or alternate names GNUMakefile and makefile that GNU make supports).
See What Name to Give Your Makefile in the GNU make manual.
If you want to use an alternate name (like make) then you need to tell make to use that file with the -f flag (also mentioned in that section of the manual).
make -f make
The missing separator error is caused by incorrect indentation in the makefile. Spaces instead of tabs on recipe lines, etc.
I was under the impression that targets should not have whitespace in front of them.
Also, Make treats the first target as the default target (what we traditionally call 'all'), so if 'clean' is your only target, it will get treated as the default.
I'm guessing your indentation is borked. Make is very, very specific in how files should be indented.
Your file should look like this:
CFLAGS=-wall -g
clean:
rm -f ex1
Notice how clean is all the way left in the file (has no whitespace in front of it), and how there are two tabs (represented here by 8 spaces because I have no way of representing tabs on SO...)
basically, Make is an ancient program that has very, VERY particular rules as to how things are done. Be careful and follow the indent rules as closely as you possibly can.
Related
I am trying to build a very simple kernel module but I get met with this error:
make -C /lib/modules/5.16.14-051614-generic/build M=/home/nanyo/Documents /ProgrammingEnvs/LinuxKernelDriver modules
make[1]: Entering directory '/usr/src/linux-headers-5.16.14-051614-generic'
make[2]: *** No rule to make target '/home/nanyo/Documents/ProgrammingEnvs/LinuxKernelDriver/hi.o', needed by '/home/nanyo/Documents/ProgrammingEnvs/LinuxKernelDriver/hi.mod'. Stop.
make[1]: *** [Makefile:1852: /home/nanyo/Documents/ProgrammingEnvs/LinuxKernelDriver] Error 2
make[1]: Leaving directory '/usr/src/linux-headers-5.16.14-051614-generic'
make: *** [Makefile:4: all] Error 2
Here is the Makefile:
obj-m += hi.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(CURDIR) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(CURDIR) clean
Although there are similar errors on stack overflow none of them spcifically say no rule to target '.../name.o' needed by '.../name.mod'
I run make like so ~/Documents/ProgrammingEnvs/LinuxKernelDriver$ make. Attempting any of the proposed solutions from other questions with sudo and experimenting with CURDIR and PWD did not help.
I am running on Ubuntu 22.04 jammy, wiht the 5.16.14 kernel (I have to run this kernel as older ones dont seem to work well with my VERY recent hardware)
I have been trying to compile 15 lines of code for 2 days now, HELP! :)
If you ask make to build an object file like hi.o, it will look to find a source file to build the object file from. It won't look for any random source file (what if you had 20 source files? How should it figure out which one you meant?), it will look for a source file based on the name of the object file.
So if you want to compile C code into hi.o, make will look for a source file named hi.c. If you want to compile C++ code into hi.o, make will look for a source file like hi.cpp. If you want to compile Fortran, make will look for hi.f, etc.
Note that Linux systems, unlike Windows and MacOS, use case-sensitive filenames so hi.c, Hi.c, HI.c, etc. are all DIFFERENT files, and hi.o will only match the first one.
If make can't find a source file related to the name of the object file, it's not going to say "well, there's just one source file here, that must be what they meant". That kind of arbitrary behavior is a bad thing in a build tool: make does exactly what you tell it to do, and if it can't it doesn't try to guess what you meant. It gives you an error, like no rule to make target 'hi.o'.
If you wanted to use a different object and source name for some reason you CAN do it, but you have to tell make about it by writing your own explicit rule:
hi.o : mycoolfile.c
<recipe to build hi.o from mycoolfile.c>
Since there's no way the kernel build can know what source file name you might choose, you'll have to write these rules in your own makefile.
I am learning C and I am trying to call a rule that I have had to write in a makefile:
CFlAGS=-Wall -g
clean:
rm -f ex1
However when I enter the command $make clean I get the error:
make: *** No rule to make target 'clean'. Stop.
I am using Cygwin64 terminal on windows and I have stored the makefile under the name ex2.mak however it is still not working
make looks for the makefile with the name Makefile.
You can use the -f option to tell it to look somewhere else, like so:
make -f ex2.mak clean
or you can rename the makefile to Makefile.
Most beginners' problems with makefiles is: The command (in your case the line containing "rm..." does not begin with a real tab character. If it doesn't, the makefile will not be correctly interpreted.
If you write a makefile, make sure your editor does not convert tabs to spaces and also make sure that you don't type spaces instead of tab characters. Other than that, the makefile looks O.K. to me so far.
I have a small C program that just computes Fibonacci. I have make file to build the file, and when I call make, I get the message make: *** No targets specified and no makefile found. Stop.. If I call make clean, I get make: *** No rule to make target `clean'. Stop. but it seems to see a makeFile (I think). I'm pretty lost and need help.
Here's the text of the make file:
CC=gcc
all: fibonacci
fibonacci: fibonacci.c
$(CC) -pthread -o fib.exe
clean:
rm fib.e xe
rename your makefile to Makefile or use make -f <whatever_name_you_like>. Remember that in unix-like systems file names are often case-sensitive (not in all types of filesystems but in many)
Refer this answer No targets specified and no makefile found
By default, when make looks for the makefile, it tries the following names, in order: GNUmakefile, makefile and Makefile.
You can also try make all and read
What Name to Give Your Makefile
Where do we put the all in a Makefiles?
I had a similar question found earlier, but I needed a little bit more details. I also looked at the GNU make manual, but got lost in the mountain of documentation. I tried the googles, but didn't find a good example. So, I did what was my last resort and tried to figure it out by hacking at a Makefile myself. I have:
CC=gcc
CFLAGS=-Wall -g
clean:
rm -f all: ex1
This didn't compile my ex1 in C. Also, if I wanted to add more to this make file. Like ex1, ex2, to exercise whatever. Would I just put the all at the top and repeat the
rm - f whatever
line below clean?
Appreciate your help and assistance. Patience appreciated too.
all is actually nothing special, just a target name commonly used. To make it work best, it should be the first target in the file. This makes it the default target, and gmake works the same as gmake all.
Normally, the all target has dependencies, which are the things which need to be built. E.g.
all: myexe
rm is related to the clean target (which is also nothing special, just a name commonly used). You define it this way:
clean:
rm -f myexe
This makes it delete myexe when gmake clean is run. If you makefile builds other files, they should also be listed there.
There's a lot more to know about makefiles. Normally you would use variables and template rules, which help you avoid repeating yourself. But this is far more than a simple answer can describe.
I am going through an eg pgm to create a make file.
http://mrbook.org/tutorials/make/
My folder eg_make_creation contains the following files,
desktop:~/eg_make_creation$ ls
factorial.c functions.h hello hello.c main.c Makefile
Makefile
# I am a comment, and I want to say that the variable CC will be
# the compiler to use.
CC=gcc
# Hwy!, I am comment no.2. I want to say that CFLAGS will be the
#options I'll pass to the compiler
CFLAGS=-c -Wall
all:hello
hello:main.o factorial.o hello.o
$(CC) main.o factorial.o hello.o -o hello
main.o:main.c
$(CC) $(CFLAGS) main.c
factorial.o:factorial.c
$(CC) $(CFLAGS) factorial.c
hello.o:hello.c
$(CC) $(CFLAGS) hello.c
clean:
rm -rf *o hello
error:
desktop:~/eg_make_creation$ make all
make: Nothing to be done for `all'.
Please help me understand to compile this program.
Sometimes "Nothing to be done for all" error can be caused by spaces before command in makefile rule instead of tab. Please ensure that you use tabs instead of spaces inside of your rules.
all:
<\t>$(CC) $(CFLAGS) ...
instead of
all:
$(CC) $(CFLAGS) ...
Please see the GNU make manual for the rule syntax description: https://www.gnu.org/software/make/manual/make.html#Rule-Syntax
Remove the hello file from your folder and try again.
The all target depends on the hello target. The hello target first tries to find the corresponding file in the filesystem. If it finds it and it is up to date with the dependent files—there is nothing to do.
When you just give make, it makes the first rule in your makefile, i.e "all". You have specified that "all" depends on "hello", which depends on main.o, factorial.o and hello.o. So 'make' tries to see if those files are present.
If they are present, 'make' sees if their dependencies, e.g. main.o has a dependency main.c, have changed. If they have changed, make rebuilds them, else skips the rule. Similarly it recursively goes on building the files that have changed and finally runs the top most command, "all" in your case to give you a executable, 'hello' in your case.
If they are not present, make blindly builds everything under the rule.
Coming to your problem, it isn't an error but 'make' is saying that every dependency in your makefile is up to date and it doesn't need to make anything!
Make is behaving correctly. hello already exists and is not older than the .c files, and therefore there is no more work to be done. There are four scenarios in which make will need to (re)build:
If you modify one of your .c files, then it will be newer than hello, and then it will have to rebuild when you run make.
If you delete hello, then it will obviously have to rebuild it
You can force make to rebuild everything with the -B option. make -B all
make clean all will delete hello and require a rebuild. (I suggest you look at #Mat's comment about rm -f *.o hello
I think you missed a tab in 9th line.
The line following all:hello must be a blank tab. Make sure that you have a blank tab in 9th line. It will make the interpreter understand that you want to use default recipe for makefile.
That is not an error; the make command in unix works based on the timestamps. I.e let's say if you have made certain changes to factorial.cpp and compile using make then make shows
the information that only the cc -o factorial.cpp command is executed. Next time if you execute the same command i.e make without making any changes to any file with .cpp extension the compiler says that the output file is up to date. The compiler gives this information until we make certain changes to any file.cpp.
The advantage of the makefile is that it reduces the recompiling time by compiling the only files that are modified and by using the object (.o) files of the unmodified files directly.
Using the comment from Paul R, I found that
make clean
followed by
make
or
make all
fixed my problem.
I arrived at this peculiar, hard-to-debug error through a different route. My trouble ended up being that I was using a pattern rule in a build step when the target and the dependency were located in distinct directories. Something like this:
foo/apple.o: bar/apple.c $(FOODEPS)
%.o: %.c
$(CC) $< -o $#
I had several dependencies set up this way, and was trying to use one pattern recipe for them all. Clearly, a single substitution for "%" isn't going to work here. I made explicit rules for each dependency, and I found myself back among the puppies and unicorns!
foo/apple.o: bar/apple.c $(FOODEPS)
$(CC) $< -o $#
Hope this helps someone!
I was trying to install libuv on Ubuntu and i also got the error make: Nothing to be done for 'all'. As i see it, using make gives two ways to solve the problem, one for check and one for install. But i found a workaround
still use the sudo make check command - it helps to read all the error messages before deciding on further actions. Basically, i've introduced a regression that makes the update workaround inefficient. This error comes from make however, the workaround from install fixes this, just try to run sudo make install and see what happens.
The make command will be a local optimization at the expense of the overall result of check/install - c'est ma façon de parler.
I believe i have narrowed down the problem considerably: in the first case after check i have "FAIL: test/run-tests" and in the second after install i get "specify the full pathname of the library, or use the '-LLIBDIR'" This argument to check/install can be a list object to store information about completed installations.
So install reports partial success when nothing actually happened.
Try running the commands from root:
cd your_program
sh autogen.sh
./configure
make
make check
make install
And then he writes that the installation was successful:
Libraries have been installed in:
/usr/local/lib
In your case, I strongly feel the only and simple problem you had is that you only preprocessed your app. You did so by having the flag -c under CFLAGS.