Testbench For Entitiy with package - VHDL - package

Question

I have problems in creating a testbench for my test module that used package.
The package just contains a block of array which is accessed in different process.
-------------------- Package ---------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package my_array_pkg is
type my_array is array ( 0 to 9) of std_logic_vector(3 downto 0);
end my_array_pkg;
And the top entity.
----------------- TOP ENTITY -------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.my_array_pkg.all;
use IEEE.NUMERIC_STD.ALL;
entity pkt_top is
Port ( sys_clk : IN STD_LOGIC;
RESET : IN STD_LOGIC;
AN_EN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Seg_Cathodes : out Std_logic_Vector(6 downto 0)
);
end pkt_top;
architecture Behavioral of pkt_top is
SIGNAL CLK1HZ, CLK256HZ : STD_LOGIC;
signal my_digit : my_array;
COMPONENT Clock_1Hz is
Port ( Sys_clk : in STD_LOGIC;
Reset : in std_logic;
C_256Hz : out std_logic;
C_1Hz : out std_logic
);
end COMPONENT;
COMPONENT Array_Count is
Port ( C_1Hz : in std_logic;
reset : in std_logic;
digit : out my_array
);
end COMPONENT;
COMPONENT Display_Driver is
Port ( Reset : in std_logic;
c256Hz : in std_logic;
C_1Hz : in std_logic;
digit_in : in my_array;
Seg_Cathodes : out Std_logic_vector(6 downto 0);
An_En : out std_logic_vector(3 downto 0)
);
end COMPONENT;
begin
C1 : Clock_1Hz -- Gives two clock divisions.
PORT MAP ( SYS_CLK, RESET,CLK256HZ, CLK1HZ);
C2 : Array_Count -- Initialize array with some numbers on every 1Hz edge
PORT MAP ( CLK1HZ, RESET, my_digit);
C3 : Display_Driver -- Dispaly the numbers on seven segments with 256Hz switching time between segments.
PORT MAP (RESET , CLK256HZ, CLK1HZ, my_digit, SEG_CATHODES, AN_EN);
end Behavioral;
The code is synthesizable and works on BASYS2 board, However I cannot simulate it via a testbench.
--------------------My TestBench -------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.my_array_pkg.all;
ENTITY pkg_tb IS
END pkg_tb;
ARCHITECTURE behavior OF pkg_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pkt_top
PORT(
sys_clk : IN std_logic;
RESET : IN std_logic;
AN_EN : OUT std_logic_vector(3 downto 0);
array_test : INOUT my_array;
Seg_Cathodes : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal sys_clk : std_logic := '0';
signal RESET : std_logic := '0';
signal my_digit : my_array;
--Outputs
signal AN_EN : std_logic_vector(3 downto 0);
signal Seg_Cathodes : std_logic_vector(6 downto 0);
-- Clock period definitions
constant sys_clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pkt_top PORT MAP (
sys_clk => sys_clk,
RESET => RESET,
AN_EN => AN_EN,
array_test => my_digit,
Seg_Cathodes => Seg_Cathodes
);
-- Clock process definitions
sys_clk_process :process
begin
sys_clk <= '0';
wait for sys_clk_period/2;
sys_clk <= '1';
wait for sys_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
-- insert stimulus here
wait;
end process;
END;
---------------------------------------------------------------
When simulate the ISIM gives an error about the 'array_test' not being availabe in the Top entity, and if this is removed the simulation remains blank.
Any Help about the testbench please.

Answer 1

I can't see a port named "array_test"in the description of the entity pkt_top. You must declare it an an output port in pkt_top.

Answer 2

Another way to avoid errors in testbench is to delete the .vhd file of testbench and create a new one for the entity you want to simulate.
In addition to, every time you edit the port of your top entity, you can delete the old and create a new testbench or edit the component of the same entity in your testbench.