Makefile: two different executables taking two overlapping subsets of code - c

Question

This is my situation, I am trying to write a Makefile for my c program, it has these components --
2 Headers:
src/header1.h
src/header2.h
N Sources:
src/src1.c
src/src2.c
src/src3.c ...
src/srcn.c
2 Mains:
src/main1.c
src/main2.c
main1.c and main2.c takes all the same src*.c and header*.h files, but in a different way. It would be really nice if I could write my Makefile in this way --
CC := gcc
INCLUDES := $(wildcard src/*.h)
SRC1 := all src*.c sources and main1.c (not main2.c)
SRC2 := all src*.c sources and main2.c (not main1.c)
IFLAGS := $(addprefix -I/,$(INCLUDES))
CFLAGS := -g -Wall -pedantic -std=gnu99 $(IFLAGS)
LDFLAGS := -lm
OBJS1 := all objects from src*.c (i.e. src*.o) and main1.o
OBJS1 := all objects from src*.c (i.e. src*.o) and main2.o
APP1 := app1
APP2 := app2
all: $(APP1) $(APP2)
$(APP1): $(OBJS1)
$(CC) $(CFLAGS) $^ -o $# $(LDFLAGS)
$(APP2): $(OBJS2)
$(CC) $(CFLAGS) $^ -o $# $(LDFLAGS)
$(OBJS1): $(SRC1)
$(CC) $(CFLAGS) -o $# -c $<
$(OBJS2): $(SRC2)
$(CC) $(CFLAGS) -o $# -c $<
clean:
rm $(OBJS1)
rm $(OBJS2)
rm $(APP1)
rm $(APP2)
How do I write the target/prerequisites rule for $SRC1, $SRC2, $OBJS1 and $OBJS2 above ?

Answer 1

COMMON = \
src1.c \
src2.c \
... \
srcn.c
MAIN1 = main1.c
MAIN2 = main2.c
COMOBJ = ${COMMON:.c=.o}
OBJS1 = ${MAIN1:.c=.o} ${COMOBJ}
OBJS2 = ${MAIN2:.c=.o} ${COMOBJ}
I often write macros such as MAIN1.c = main1.c as POSIX requires make to support that notation (and all the variants I've encountered do support it). But beware the vim doesn't think the macro names like that are kosher (which is a bug in vim's recognition of make macros). Then I'd write:
COMMON.c = ...
MAIN1.c = main1.c
...
FILES1.o = ${MAIN1.c:.c=.o} ${COMMON.c:.c=.o}
etc. Not everyone likes this notation.

Answer 2

You should be fine with just a list of objects
OBJS = src1.o src2.o #... etc
main1: main1.o $(OBJS)
main2: main2.o $(OBJS)
and let make use your provided CC, CFLAGS, and LDFLAGS to figure out the rest