How to connect 8-bit GPIO "General-Purpose Input/Output" with 3 8-bit timers (Timer0, Timer1, PWM) as multiplexer.
GPIO get the 3 Timers outputs as an input, choose between them. It's output is one of the 3 inputs it had as a multiplexer?
How can I make this connection in design also in VHDL by coding?
What will be the functionality of each pin in GPIO?
Thanks.
*-- Assuming you have logic to produce the mux selects: mux_sel(1 downto 0) :*
C1: PROCESS (timer0, timer1, pwm, mux_sel) IS
BEGIN
CASE mux_sel IS
WHEN "00" => gpio_in <= timer0;
WHEN "01" => gpio_in <= timer1;
WHEN "10" => gpio_in <= pwm;
WHEN OTHERS => NULL;
END CASE;
END PROCESS C1;
-- Even simpler:
gpio_in <= timer0 WHEN mux_sel = "00" ELSE
timer1 WHEN mux_Sel = "01" ELSE
pwm;
Related
I am testing an interoperability between modems. one of my modem did support JANUS and I believe UnetStack base Subnero Modem Phy[3] also support JANUS. How can i send and record JANUS signal which i can use for preliminary testing for other modem ? Can someone please provide basic snippet ?
UnetStack indeed has an implementation of JANUS that is, by default, configured on phy[3].
You can check this on your modem (the sample outputs here are from unet audio SDOAM, and so your modem parameters might vary somewhat):
> phy[3]
« PHY »
[org.arl.unet.phy.PhysicalChannelParam]
fec = 7
fecList ⤇ [LDPC1, LDPC2, LDPC3, LDPC4, LDPC5, LDPC6, ICONV2]
frameDuration ⤇ 1.1
frameLength = 8
janus = true
[org.arl.yoda.FhbfskParam]
chiplen = 1
fmin = 9520.0
fstep = 160.0
hops = 13
scrambler = 0
sync = true
tukey = true
[org.arl.yoda.ModemChannelParam]
modulation = fhbfsk
preamble = (2400 samples)
threshold = 0.0
(I have dropped a few parameters that are not relevant to the discussion here to keep the output concise)
The key parameters to take note of:
modulation = fhbfsk and janus = true setup the modulation for JANUS
fmin = 9520.0, fstep = 160.0 and hops = 13 are the modulation parameters to setup fhbfsk as required by JANUS
fec = 7 chooses ICONV2 from the fecList, as required by JANUS
threshold = 0.0 indicates that reception of JANUS frames is disabled
NOTE: If your modem is a Subnero M25 series, the standard JANUS band is out of the modem's ~20-30 kHz operating band. In that case, the JANUS scheme is auto-configured to a higher frequency (which you will see as fmin in your modem). Do note that this frequency is important to match for interop with any other modem that might support JANUS at a higher frequency band.
To enable JANUS reception, you need to:
phy[3].threshold = 0.3
To avoid any other detections from CONTROL and DATA packets, we might want to disable those:
phy[1].threshold = 0
phy[2].threshold = 0
At this point, you could make a transmission by typing phy << new TxJanusFrameReq() and put a hydrophone next to the modem to record the transmitted signal as a wav file.
However, I'm assuming you would prefer to record on the modem itself, rather than with an external hydrophone. To do that, you can enable the loopback mode on the modem, and set up the modem to record the received signal:
phy.loopback = true # enable loopback
phy.fullduplex = true # enable full duplex so we can record while transmitting
phy[3].basebandRx = true # enable capture of received baseband signal
subscribe phy # show notifications from phy on shell
Now if you do a transmission, you should see a RxBasebandSignalNtf with the captured signal:
> phy << new TxJanusFrameReq()
AGREE
phy >> RxFrameStartNtf:INFORM[type:#3 rxTime:492455709 rxDuration:1100000 detector:0.96]
phy >> TxFrameNtf:INFORM[type:#3 txTime:492456016]
phy >> RxJanusFrameNtf:INFORM[type:#3 classUserID:0 appType:0 appData:0 mobility:false canForward:true txRxFlag:true rxTime:492455708 rssi:-44.2 cfo:0.0]
phy >> RxBasebandSignalNtf:INFORM[adc:1 rxTime:492455708 rssi:-44.2 preamble:3 fc:12000.0 fs:12000.0 (13200 baseband samples)]
That notification has your signal in baseband complex format. You can save it to a file:
save 'x.txt', ntf.signal, 2
To convert to a wav file, you'll need to load this signal and convert to passband. Here's some example Python code to do this:
import numpy as np
import scipy.io.wavfile as wav
import arlpy.signal as asig
x = np.genfromtxt('x.txt', delimiter=',')
x = x[:,0] + 1j * x[:,1]
x = asig.bb2pb(x, 12000, 12000, 96000)
wav.write('x.wav', 96000, x)
NOTE: You will need to replace the fd and fc of 12000 respectively, by whatever is the fs and fc fields in your modem's RxBasebandSignalNtf. For Unet audio, it is 12000 for both, but for Subnero M25 series modems it is probably 24000.
Now you have your wav file at 96 kSa/s!
You could also plot a spectrogram to check if you wanted to:
import arlpy.plot as plt
plt.specgram(x, fs=96000)
I have an issue while recording the signal. Modem refuse to send the JANUS frame. It looks like something is not correctly set on my end, specially fmin = 12000.0 , fstep = 160.0 and hops = 13. The Actual modem won't let me set the fmin to 9520.0 and automatically configured on lowest fmin = 12000. How can i calculate corresponding parameters for fmin=12000.
Although your suggestion do work on the unet audio.
Here is my modem logs:
> phy[3]
« PHY »
[org.arl.unet.DatagramParam]
MTU ⤇ 0
RTU ⤇ 0
[org.arl.unet.phy.PhysicalChannelParam]
dataRate ⤇ 64.0
errorDetection ⤇ true
fec = 7
fecList ⤇ [LDPC1, LDPC2, LDPC3, LDPC4, LDPC5, LDPC6, ICONV2]
frameDuration ⤇ 1.0
frameLength = 8
janus = true
llr = false
maxFrameLength ⤇ 56
powerLevel = -10.0
[org.arl.yoda.FhbfskParam]
chiplen = 1
fmin = 12000.0
fstep = 160.0
hops = 13
scrambler = 0
sync = true
tukey = true
[org.arl.yoda.ModemChannelParam]
basebandExtra = 0
basebandRx = true
modulation = fhbfsk
preamble = (2400 samples)
test = false
threshold = 0.3
valid ⤇ false
> phy << new TxJanusFrameReq()
REFUSE: Frame type not setup correctly
phy >> FAILURE: Timed out
I have the following interface and uvm_monitor (run_phase shown below).
The DUT signals are "x" for sometime. When I print the signals, in my monitor, they are captured as "x". Great.
Next, DUT signals show a valid value (the first time). When I print the signals, in my monitor, they are captured as with valid values. Great.
Next, DUT updates the all the three signals to the next value, and at time stamp 134, mirror_byte_wr_en remains to be 0 but expected to be at 0xffff..
Any idea, why? Appreciate your thoughts and inputs.
Example output from the log:
UVM_INFO snp_decomp_snpd_egress_monitor.sv(65) # 122:
uvm_test_top.m_snp_decomp_env.snpd_egress[0].m_monitor
[snp_decomp_snpd_egress_monitor] mirror_data =
0x00006c61776e694720616669617a7548
UVM_INFO snp_decomp_snpd_egress_monitor.sv(71) # 122:
uvm_test_top.m_snp_decomp_env.snpd_egress[0].m_monitor
[snp_decomp_snpd_egress_monitor] mirror_byte_wr_en = 0xffff
UVM_INFO snp_decomp_snpd_egress_monitor.sv(76) # 122:
uvm_test_top.m_snp_decomp_env.snpd_egress[0].m_monitor
[snp_decomp_snpd_egress_monitor] mirror_wr_addr = 0x00000
UVM_INFO snp_decomp_snpd_egress_monitor.sv(65) # 134:
uvm_test_top.m_snp_decomp_env.snpd_egress[0].m_monitor
[snp_decomp_snpd_egress_monitor] mirror_data =
0x3c10xxxxxxxxxxxxxxxx616c00000000
UVM_INFO snp_decomp_snpd_egress_monitor.sv(71) # 134:
uvm_test_top.m_snp_decomp_env.snpd_egress[0].m_monitor
[snp_decomp_snpd_egress_monitor] mirror_byte_wr_en = 0x0000
UVM_INFO snp_decomp_snpd_egress_monitor.sv(76) # 134:
uvm_test_top.m_snp_decomp_env.snpd_egress[0].m_monitor
[snp_decomp_snpd_egress_monitor] mirror_wr_addr = 0x00010
enter code here
task run_phase(uvm_phase phase);
snp_decomp_snpd_egress_transaction tr;
tr = snp_decomp_snpd_egress_transaction ::type_id::create("tr");
forever begin
#(vif.egress.egress_cb);
fork
begin
// # (vif.egress.egress_cb);
tr.mirror_data = vif.egress.egress_cb.mirror_wr_data;
`uvm_info(get_type_name(),$sformatf("mirror_data = 0x%x\n", vif.egress.egress_cb.mirror_wr_data),UVM_LOW);
end
begin
// # (vif.egress.egress_cb);
tr.mirror_wr_byte_en = vif.egress.egress_cb.mirror_byte_wr_en;
`uvm_info(get_type_name(),$sformatf("mirror_byte_wr_en = 0x%x\n", vif.egress.egress_cb.mirror_byte_wr_en),UVM_LOW);
end
begin
// # (vif.egress.egress_cb);
tr.mirror_wr_addr = vif.egress.egress_cb.mirror_wr_addr;
`uvm_info(get_type_name(),$sformatf("mirror_wr_addr = 0x%x\n", vif.egress.egress_cb.mirror_wr_addr),UVM_LOW);
end
join
end
endtask : run_phase
interface snp_decomp_snpd_egress_intf(input logic clock, input logic reset);
logic [127:0] mirror_wr_data;
logic [15:0] mirror_byte_wr_en;
logic [18:0] mirror_wr_addr;
modport DUT (
input clock,
input reset,
output mirror_wr_data,
output mirror_byte_wr_en,
output mirror_wr_addr
); // modport DUT
clocking egress_cb #(posedge clock);
input mirror_wr_data;
input mirror_byte_wr_en;
input mirror_wr_addr;
endclocking: egress_cb
modport egress(clocking egress_cb);
endinterface : snp_decomp_snpd_egress_intf
enter image description here
It is correct behaviour because sample values in clocking block were taken from the previous clock cycle. It depends on SystemVerilog time step semantics.
begin
#(vif.egress.egress_cb);
`uvm_info(get_type_name(), $sformatf("mirror_byte_wr_en: value from previous cycle - 'h%0h, value from current cycle - 'h%0h",
vif.egress.egress_cb.mirror_byte_wr_en, vif.egress.mirror_byte_wr_en), UVM_LOW)
end
For full understanding - LRM 14.13.
Best regards, Maksim.
im implementing a digital clock with verilog. I count clk's and so count seconds. Then i sent outputs to seven segment display. My second display works perfectly, but minute's doesnt work . Some times , it displays like , in first increase 60, in second 2 , third 45 60 anything, fourth 4.
I created split module which takes 1 input give 2 output. Like
if input = 56 , output 1 = 5 , output 2=6 . Works perfect in simulation and for second.
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:36:40 11/05/2015
// Design Name:
// Module Name: Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top(input clk,reset,input in0, in1, in2, in3,output a, b, c, d, e, f, g, dp,output [3:0] an
);
wire [3:0] minLeft,minRight;
wire [3:0] secLeft,secRight;
wire [6:0] second,minute;
wire[4:0] hour;
wire newDay;
split_output sec(second,secLeft,secRight);
split_output split(minute,minLeft,minRight);
Clock timer(clk,second,minute,hour,newDay);
sevenseg decoder(clk,reset,minLeft,minRight,secLeft,secRight,a,b,c,d,e,f,g,dp,an);
endmodule
CLOCK MODULE
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:26:35 11/05/2015
// Design Name:
// Module Name: Clock
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Clock(input clk,output [6:0] second,minute,output [4:0] hour,output reg newDay
);
//Clock counter for second
reg [25:0]cnt_clk=0;
//Second counter
reg [6:0]cnt_second=0;
//Minutes counter
reg [6:0]cnt_minute=0;
//Hour counter
reg [4:0]cnt_hour=0;
assign second=cnt_second;
assign minute=cnt_minute;
assign hour=cnt_hour;
//COUNT CLOCK, INCREASE SECOND
always#(*)
begin
// IF CLOCK COUNT İS 1 SECOND
if(cnt_clk==26'd5000000)
begin
cnt_clk=26'd0;
// IF SECOND COUNT İS 60, RESET İT
if(cnt_second==7'b0111100)
begin
cnt_second<=7'b0000000;
end
else
begin
cnt_second<=cnt_second+1;
end
end
else
begin
cnt_clk=cnt_clk+1;
end
end
// UPDATE MİNUTES, AS SECONDS INCREASE
always#(cnt_second)
begin
//IF ITS 1 MINUTES
if(cnt_second==7'd60)
begin
if(cnt_minute==7'd60)
begin
cnt_minute<=0;
end
else
begin
cnt_minute=cnt_minute+1;
end
end
end
//UPDATE HOURS,AS MİNUTES INCREASE
always#(cnt_minute)
begin
//IF ITS 60 MINUTES
if(cnt_minute==7'b0111100)
begin
if(cnt_hour==5'b11000)
begin
cnt_hour<=5'b00000;
end
else
begin
cnt_hour<=cnt_hour+1;
end
end
end
// IF THE DAY İS OVER
always#(cnt_hour)
begin
if(cnt_hour==5'b11000)
begin
newDay=1;
end
else
begin
newDay=0;
end
end
endmodule
SPLİT MODULE
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:51:22 11/09/2015
// Design Name:
// Module Name: split_output
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module split_output(input [7:0] total,output reg[3:0] left,right
);
always#(total)
begin
if(total>=8'b00110010&&total<8'b00111100)
begin
assign left=4'b0101;
assign right=total-50;
end
if(total>=8'b00101000&&total<8'b00110010)
begin
assign left=4'b0100;
assign right=total-40;
end
if(total>=8'b00011110&&total<8'b00101000)
begin
assign left=4'b0011;
assign right=total-30;
end
if(total>=8'b00010100&&total<8'b00011110)
begin
assign left=4'b0010;
assign right=total-20;
end
if(total>=8'b00001010&&total<8'b00010100)
begin
assign left=4'b0001;
assign right=total-10;
end
if(total<8'b00001010)
begin
assign left=0;
assign right=total;
end
if(total==8'b00111100)
begin
assign left=4'b0110;
assign right=0;
end
end
endmodule
7seg decoder- i found in that site- it works perfect( THANKS TO WHO PUBLİSHED AGAİN)
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:31:47 11/05/2015
// Design Name:
// Module Name: sevenseg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sevenseg(
input clock, reset,
input [3:0] in0, in1, in2, in3, //the 4 inputs for each display
output a, b, c, d, e, f, g, dp, //the individual LED output for the seven segment along with the digital point
output [3:0] an // the 4 bit enable signal
);
localparam N = 18;
reg [N-1:0]count; //the 18 bit counter which allows us to multiplex at 1000Hz
always # (posedge clock or posedge reset)
begin
if (reset)
count <= 0;
else
count <= count + 1;
end
reg [6:0]sseg; //the 7 bit register to hold the data to output
reg [3:0]an_temp; //register for the 4 bit enable
always # (*)
begin
case(count[N-1:N-2]) //using only the 2 MSB's of the counter
2'b00 : //When the 2 MSB's are 00 enable the fourth display
begin
sseg = in0;
an_temp = 4'b1110;
end
2'b01: //When the 2 MSB's are 01 enable the third display
begin
sseg = in1;
an_temp = 4'b1101;
end
2'b10: //When the 2 MSB's are 10 enable the second display
begin
sseg = in2;
an_temp = 4'b1011;
end
2'b11: //When the 2 MSB's are 11 enable the first display
begin
sseg = in3;
an_temp = 4'b0111;
end
endcase
end
assign an = an_temp;
reg [6:0] sseg_temp; // 7 bit register to hold the binary value of each input given
always # (*)
begin
case(sseg)
4'd0 : sseg_temp = 7'b1000000; //to display 0
4'd1 : sseg_temp = 7'b1111001; //to display 1
4'd2 : sseg_temp = 7'b0100100; //to display 2
4'd3 : sseg_temp = 7'b0110000; //to display 3
4'd4 : sseg_temp = 7'b0011001; //to display 4
4'd5 : sseg_temp = 7'b0010010; //to display 5
4'd6 : sseg_temp = 7'b0000010; //to display 6
4'd7 : sseg_temp = 7'b1111000; //to display 7
4'd8 : sseg_temp = 7'b0000000; //to display 8
4'd9 : sseg_temp = 7'b0010000; //to display 9
default : sseg_temp = 7'b0111111; //dash
endcase
end
assign {g, f, e, d, c, b, a} = sseg_temp; //concatenate the outputs to the register, this is just a more neat way of doing this.
// I could have done in the case statement: 4'd0 : {g, f, e, d, c, b, a} = 7'b1000000;
// its the same thing.. write however you like it
assign dp = 1'b1; //since the decimal point is not needed, all 4 of them are turned off
endmodule
MY UCF
NET "reset" LOC = "a7";
# Pin assignment for 7-segment displays
NET "a" LOC = "l14" ;
NET "b" LOC = "h12" ;
NET "c" LOC = "n14" ;
NET "d" LOC = "n11" ;
NET "e" LOC = "p12" ;
NET "f" LOC = "l13" ;
NET "g" LOC = "m12" ;
NET "dp" LOC = "n13" ;
NET "an[0]" LOC = "k14";
NET "an[1]" LOC = "m13";
NET "an[2]" LOC = "j12";
NET "an[3]" LOC = "f12";
# Pin assignment for clock
NET "clk" LOC = "b8";
Blocking (=) vs non-blocking (<=) been answered may times:
How to interpret blocking vs non blocking assignments in Verilog?
Verilog Blocking Assignment
Nonblocking Assignments in Verilog Synthesis, Coding
Styles That Kill! (Cliff Cummings paper)
Latches are inferred when a reg is not assigned in all possible branches within a otherwise conbinational block. If you want latches, put them in a separate always block, away from the combinational logic, use non-blocking (<=) assignments, and keep them as simple assignments. Doing so will remove the confusion of what is intended to be decoding logic, level sensitive latches, and edge sensitive flip-flops. Combinational loops are another hazard. This is where you get different results if you run the same combinational block two or more times with the same inputs in the same time stamp and get different outputs.
When it comes to RTL coding style, I typically follow Cliff Cummings' recommendations, such as:
The Fundamentals of Efficient Synthesizable Finite State Machine
Design
Coding And Scripting Techniques For FSM Designs With
Synthesis-Optimized, Glitch-Free Outputs
There are additional links to useful Verilog/SystemVerilog references in my profile. I personally do not like nested conditional statements (?:). From experience, I get better synthesis results using case statements when there are more then two possibilities.
Here is an incomplete example how I would code Clock and split_output. I'll leave the rest for you figure out and learn on your own.
module Clock(
input clk,
output reg [5:0] second, minute,
output reg [3:0] hour,
output reg newDay
);
// ... declare local regs
// SYNCHRONOUS ASSIGNMENTS
always #(posedge clk) begin
cnt_clk <= next_cnt_clk;
second <= next_second;
// ... other assignments
end
// COMBINATIONAL CALCULATIONS
always #* begin
// DEFAULT VALUES
next_cnt_clk = cnt_clk + 1;
next_second = second;
// ... other default
// IF CLOCK COUNT İS 1 SECOND
if (next_cnt_clk == 24'd5000000) begin
next_cnt_clk = 24'd0;
next_second = second + 1;
end
// IF SECOND COUNT İS 60, RESET İT
if (next_second == 6'd60) begin
next_second = 6'd0;
next_minute = minute + 1;
end
// ... other calculations
end
endmodule
module split_output(
input [5:0] total,
output reg [3:0] left, right
);
always #* begin
if (total < 8'd10) begin
left = 4'b0000;
right = total[3:0];
end
else if (total < 8'd20) begin
left = 4'b0001;
right = total-10;
end
// ... other 'else if'
else begin // final is 'else'
left = 4'b0110;
right = 4'b0000;
end
end
endmodule
Whats the best way to perform a port map for each bit in a vector? Say I have a vector representing a series of buttons, and wish to debounce each one using a bebounce module, how should I go about that?
Right now I have the following, but I believe there should be a better way
entity ButtonDebouncer is
Port (
clock : in std_logic;
buttons : in std_logic_vector(0 to 5);
--{ more stuff }
);
end ButtonDebouncer;
architecture Behavioral of ButtonDebouncer is
signal bufferedButtons : std_logic_vector(0 to 5) := (others => '0');
begin
c1: entity debounce port map (Clock, buttons(0), bufferedButtons(0));
c2: entity debounce port map (Clock, buttons(1), bufferedButtons(1));
c3: entity debounce port map (Clock, buttons(2), bufferedButtons(2));
c4: entity debounce port map (Clock, buttons(3), bufferedButtons(3));
c5: entity debounce port map (Clock, buttons(4), bufferedButtons(4));
c6: entity debounce port map (Clock, buttons(5), bufferedButtons(5));
--{ Do stuff with debounced buttons }
end Behavioral;
For generate would be a good candidate construct here.
entity ButtonDebouncer is
Port (
clock : in std_logic;
buttons : in std_logic_vector(0 to 5);
--{ more stuff }
);
end ButtonDebouncer;
architecture Behavioral of ButtonDebouncer is
signal bufferedButtons : std_logic_vector(0 to 5) := (others => '0');
begin
debouncers: for i in 0 to 5 generate
c1: entity debounce port map (Clock, buttons(i), bufferedButtons(i));
end generate;
--{ Do stuff with debounced buttons }
end Behavioral;
Travis' solution is a good starting point.
I would go one step further and implement a debounce module for multiple bits. So you can pass a whole button vector to this module.
entity debounce is
generic (
BITS : POSITIVE
);
port (
Clock : STD_LOGIC;
Input : STD_LOGIC_VECTOR(BITS - 1 downto 0);
Output : STD_LOGIC_VECTOR(BITS - 1 downto 0)
)
end entity;
architecture rtl of debounce is
-- define 'global' signals here (per instance)
begin
genDebounce : for i in 0 to BITS - 1 generate
-- define 'local' signals here (per debounce circuit)
begin
-- debounce circuit
end generate;
end architecture;
Usage:
debButtons : entity work.debounce
generic map (
BITS => buttons'length
)
port map (
Clock => Clock,
Input => Buttons,
Output => bufferedButtons
);
Question: Make Calendar Which Shows Month Number and Days of Month ?
Write Both in Combinational and Sequential VHDL Constructs ?
I am new on this VHDL and i have a quiz on Monday .. Anyone have any idea about where to start and how to start writing the programming in VHDL ?
Any help will be greatly appreciated ..
Thanks
Here is something to get you started with your assignment. It accepts the binary value of month, 1-12, and if it is a leap year or not, and outputs the number of days in that month. This is done without a clock (combinatorial/asynchronous logic).
I think you can take this and determine the best way to use sequential statements to create an alternative implementation based on what you assignment is asking for.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Days_In_Month is
port (
I_MONTH : in unsigned(3 downto 0);
I_LEAP_YEAR : in std_logic;
O_DAYS_IN_MONTH : out unsigned(4 downto 0)
);
end entity Days_In_Month;
architecture Days_In_Month_combinatorial of Days_In_Month is
signal month_30d : std_logic;
signal month_28d : std_logic;
signal month_31d : std_logic;
signal month_29d : std_logic;
begin
month_30d <= '1' when I_MONTH = 9 or
I_MONTH = 4 or
I_MONTH = 6 or
I_MONTH = 11
else '0';
month_28d <= '1' when I_MONTH = 2 and
I_LEAP_YEAR = '0'
else '0';
month_29d <= '1' when I_MONTH = 2 and
I_LEAP_YEAR = '1'
else '0';
month_31d <= '1' when month_30d = '0' and
month_28d = '0' and
month_29d = '0'
else '0';
O_DAYS_IN_MONTH <= to_unsigned(30,O_DAYS_IN_MONTH'length) when month_30d = '1' else
to_unsigned(28,O_DAYS_IN_MONTH'length) when month_28d = '1' else
to_unsigned(29,O_DAYS_IN_MONTH'length) when month_29d = '1' else
to_unsigned(31,O_DAYS_IN_MONTH'length) when month_31d = '1'
else to_unsigned(0,O_DAYS_IN_MONTH'length);
end architecture Days_In_Month_combinatorial;