I have a makefile which further calls a xml converter tool. The details of the tool and makefile seems irrelevant here. Reason being, there is no problem in the overall makefile, but this xml converter tools fails and returns an error message. Since this is not a makefile error, therefore makefile doesnt stop executing rest of the code. Is there anyway we could avoid this problem? I was thinking of adding a batch file which executes that tool, and then we can call the batch file from the makefile, but then again, how will we know the batch file returned an error? Any hint would be appreciated.
PS: By avoiding the problem, I meant, that makefile should stop when the tool returns an error.
If a grep exist on your system, you could do something like the following rule:
FILE: DEP-FILE
! XMLCONVERTER $< | grep -q "YOUR ERROR STATEMENT"
In case that XMLCONVERTER prints "YOUR ERROR STATEMENT" to stdout, a make error is raised.
Related
I'm new to VeriFone development. I need to compile the RCK file. I have used the below command to do that, but the command doesn't show any output or generate file. It does nothing.
C:\eVoAps\Tools>Rck2.exe -SC:\Bill\MyApp\Source\Resource\
MyApp -OC:\Bill\MyApp\Output\RV\Files\Resource\MyApp -M
Could anyone help me to fix this issue.
First of all, you say it does nothing. Does it at least give you an error? If so, what is it?
If it does NOTHING, then make sure you have the following files in your C:\eVoAps\Tools folder:
C1.DLL
CL.EXE
MSPDB60.DLL
If you are getting an error, then I suspect it is something close to this:
C:\Bill\MyApp\Source\Resource\MyApp.RCK(28) : fatal error C1034:
devman.h: no include path set Parse Error in
file[C:\Bill\MyApp\Source\Resource\MyApp.RI]! Invalid token [eof] at
line -1 offset -1 SSYacc0105e: Error token failed, no valid token
ERROR! Aborting compilation!
The reason I say that is because I'm pretty sure you need to include the VMAC includes and template for it to work. These can be found in %EVOVMAC%\include and %EVOVMAC%\template. To include, use the -J switch:
C:\eVoAps\Tools>Rck2.exe -SC:\Bill\MyApp\Source\Resource\MyApp
-OC:\Bill\MyApp\Output\RV\Files\Resource\MyApp
-M -J%EVOVMAC%\include -J%EVOVMAC%\Template
(Naturally, this will need to all be on 1 line, but I'm breaking it up here to make it more legible)
Note that if you are using nmake, you can have the resource file generated as part of the build. My make file does that with these lines:
$(ResDir)\$(ProjectName).res : $(ResDir)\$(ProjectName).rck
$(EVOTOOLS)rck2 -S$(ResDir)\$(ProjectName) -O$(ResDir)\$(ProjectName) -M
You may have noticed that I didn't use the -J switches here. That's because I've already included those paths in my project and that is captured in my build. I believe an alternative to either of these would be
$(ResDir)\$(ProjectName).res : $(ResDir)\$(ProjectName).rck
SET INCLUDE=$(INCLUDE);$(EVOVMAC)\include;$(EVOVMAC)\template
$(EVOTOOLS)rck2 -S$(ResDir)\$(ProjectName) -O$(ResDir)\$(ProjectName) -M
although that depends on how your build is set up.
My shell script is having an issue, however, it's a bit too long to post here. Here is a link to it: http://pastebin.com/jh9fHJ2e
Does anyone have any idea why I would be getting these two errors? I'm calling it from a makefile like so:
.PHONY: compile clean
compile:
$(shell ./compile.sh)
clean:
$(shell ./clean.sh)
However, if I run it manually (`./compile.sh`), I do not get the error. What am I doing wrong? I worry that the quotes are coming from the output lines: make: Nothing to be done for 'default. due to the weird quote lapse in there, but how do I prevent that if Make is what's causing it?
Hopefully this is a reasonable, non-duplicate question. It's not the same as other similar ones as I've checked. I'm happy to remove if it's a bad question, please simply let me know.
You should not use $(shell ...) here. The shell function is like backticks in a shell script: the result of the execution is the standard output of the command invoked. If your command prints some text, that will try to be executed as a shell script.
A recipe is already run in a shell, so you don't need the shell function:
.PHONY: compile clean
compile:
./compile.sh
clean:
./clean.sh
I wish I could understand why so many people try to use the shell function in recipes like this... I feel like there must be some "intro to make" out there using very bad examples.
Generally you wouldn't create separate shell scripts, anyway: you'd put the compile and clean commands right into the recipe. What's the point of having a makefile where you type "make clean" when all it does is run a shell script, so you could just type "./clean.sh" instead and get the same behavior?
The make syntax $(shell ... ) runs a shell command and substitutes the output of the shell command into the make script at that point. So when you have a rule like
compile:
$(shell ./compile.sh)
it will run the script compile.sh and take the output of that shell script as the actions (shell commands) to run to complete the compile target. Since it looks like your compile.sh script does the actual compile, outputting messages about what it is doing, when make then tries to run those messages as shell commands, the shell barfs (giving you error messages).
i want to execute UV4 in source insight, and catch the errors and display.
the batch file context is
c:\Keil\UV4\UV4.exe -b d:\workingcopy\test_project\test.uvproj -o log
type d:\workingcopy\test_project\log
when i run the batch file, and the compile completed correct, it works fun.
but if the compile end by the error, the source insight will show ...\231 does not exist.
how to fix it ?
thanks for any help :)
Now i know where the devil is.
the error messages output by UV4, is PATH\FILE(LINE)
and the regex i use lead SI deal the line as a file.
the error line number is 231, so the SI show "231 does not exist"
In my Python scripts which call uVision I check the error level of UV4 plus I parse the build log using regex. I always used this manual for reference.
i have created (executable) binary "sample" from .c using
gcc sample.c -o sample
it's created binary named sample sucessfully.
when i run this from terminal like ./sample it display a result..
but when i run this from my tcl like exec ./sample it shows error like ./sample no such file or directory..
can anyone help me to solve the above error?
If sample in the current directory is executable, exec ./sample should work. Assuming that the binary itself does not generate that error message when it runs, of course. (Messages on stderr will become errors in Tcl by default.)
Check that puts [pwd] tells you the place you expected; if you had a cd elsewhere in your script then that relative path would no longer work. If this is the problem, use the full, absolute path to the compiled file. (You can compute this at the start of your script using file normalize sample, but you have to do this before you cd; good library packages do not use cd precisely because it is so confusing while simultaneously being usually totally unnecessary for them…)
If file exists ./sample is true (and file executable ./sample is also true, which it should be if it has just been produced by a compiler) then check immediately after the failed execution what the contents of the errorInfo and errorCode global variables are. They may give a bit more indication of what went wrong. (Or maybe not; can't tell for sure.)
I've written the below makefile:
hw2p1: hw2p1_main.o hw2p1_getit.o hw2p1_parseit.o hw2p1_moveit.o hw2p1_showit.o
gcc hw2p1_main.o hw2p1_getit.o hw2p1_parseit.o hw2p1_moveit.o hw2p1_showit.o
hw2p1_main.o: hw2p1_main.c
gcc -c hw2p1_main.c
hw2p1_getit.o: hw2p1_getit.c
gcc -c hw2p1_getit.c
hw2p1_parseit.o: hw2p1_parseit.c
gcc -c hw2p1_parseit.c
hw2p1_moveit.o: hw2p1_moveit.c
gcc -c hw2p1_moveit.c
hw2p1_showit.o: hw2p1_showit.c
gcc -c hw2p1_showit.c
The first time I tried to call make, I got the error: "make: Fatal error: unexpected end of line seen" I deleted the blank lines between targets and called make again, but this time I got " 'ake: Fatal error: Don't know how to make hw2p1_main.c"
I've compiled all of these files separately and then linked them so I know that the errors are a result of an incorrect makefile and not a result of errors in my c files.
This is the first makefile that I've ever written so I might just be doing it completely incorrectly. Either way, any suggestions on how to get rid of these errors?
This can happen when the directory is inadvertently not the one it should be so it looks like hw2p1_main.c's absence calls for a rule to create the C source file.
It could also be a filename misspelling.
You seem to be missing the -o in the linking command, though that's probably not what's on your mind yet. The immediate complaint is that make can't find that .c file. Sure it's there in the current working directory?
As a start, try a makefile which only compiles one thing:
hw2p1_moveit.o: hw2p1_moveit.c
gcc -o moveit.o -c hw2p1_moveit.c
Also, make sure that the 2nd line uses a TAB character, rather than spaces. (I have to manually set this in my editor because spaces are the only smart way to do it :)
Your Makefile is way more complicated than it needs to be. Let Make use its implicit rules. It knows how to make foo.o from foo.c, and you don't need to tell it that. Your entire Makefile can be reduced to:
OBJS = hw2p1_main.o hw2p1_getit.o hw2p1_parseit.o hw2p1_moveit.o hw2p1_showit.o
hw2p1: $(OBJS)
$(CC) $(CFLAGS) $(CPPFLAGS) $(OBJS) -o $#
As noted by others--make sure you use an actual tab for the indentation. Make is extremely picky about that.
Just a stab in the dark, but does the filename's case match? Coming from a windows/apple world, some people are surprised that unix filenames are case sensitive.
You can check this by copying the filename exactly from the error output and trying to list it, i.e. ls -l <paste>. That should also show you whether there's some control characters embedded in the filename, which could also be your problem.
This answer is almost never available! Okay, so basically I found a solution. The makefile you've written is sound. However, you have to create it in EMACS. Wierd right? I had a submission due and had written my makefile in notepad and uploaded it onto the university server, and it never ran! I tried using different variants of the code to no luck. Then in frustration I retyped the whole thing in EMACS, and it just worked. No modifications to the code. Give it a shot!
If you have made sure
1) That all files it's saying are missing are in same directory as that of makefile or otherwise as per path indicated
2) all command lines are containing tabs and not spaces (easiest way to check is to press a left arrow key at your first character and it should return to home position (0th char of line position)
Then Most of the time the problem is file format of Makefile
If you are typing a file in an editor having a PC (CR/LF) Line format then you will have to set it to just CR file format.
So, you can type the Makefile in vi or emacs or any other editor which has default file format of UNIX and it will work or set your document file format to be of UNIX type in your editor if it allows to set one.
This must work for all errors of type
'ake: Fatal error: Don't know how to make target (OR) <BR/>
'ake: Fatal error: Don't know how to make target(lastfilename in line)
Hope this helps.