I am trying to install the SCIP optimisation suite version 3.1.0
http://scip.zib.de/download.php?fname=scipoptsuite-3.1.0.tgz
The software is compiled by typing the 'make' command in the scipoptsuite-3.1.0 directory. The package contains three constituent packages (SCIP, soplex and zimpl). There is a makefile for the general package (scipoptsuite) and also a makefile for the three constituent packages. I am having great difficulties when it comes to the compilation of zimpl.
The error occurs when attempting to compile using the code within the zimpl makefile. There is an attempt to generate a library and to store object files within that library.
I am now going to provide some of the relevant code to the problem.
Here are some key definitions:
AR = ar cr
ARFLAGS =
RANLIB = ranlib
LIBBASE = blkmem.o bound.o code.o conname.o define.o elem.o entry.o \
hash.o heap.o idxset.o inst.o iread.o list.o \
load.o local.o metaio.o mmlparse2.o mmlscan.o mono.o \
mshell.o prog.o random.o rdefpar.o source.o \
setempty.o setpseudo.o setlist.o setrange.o setprod.o \
setmulti.o set4.o stmt.o stkchk.o strstore2.o symbol.o \
term2.o tuple.o vinst.o zimpllib.o
LIBDIR = lib
LIBRARY = $(LIBDIR)/lib$(LIBNAME).a
LIBNAME = $(NAME)-$(VERSION).$(BASE)
OBJDIR = obj/O.$(OSTYPE).$(ARCH).$(COMP).$(LINK).$(OPT)
LIBOBJ = $(LIBBASE) gmpmisc.o numbgmp.o
LIBXXX = $(addprefix $(OBJDIR)/,$(LIBOBJ))
And here is the key segment of code which causes the error:
$(LIBRARY): $(OBJDIR) $(LIBDIR) $(LIBXXX)
#echo "-> generating library $#"
-rm -f $(LIBRARY)
$(AR) $# $(LIBXXX) $(ARFLAGS)
$(RANLIB) $#
Which generates the following error message:
** Building ZIMPL library "mypath/scipoptsuite-3.1.0/zimpl-3.3.2/lib/libzimpl.linux.arm.gnu.opt.a".
make[2]: Entering directory `mypath/scipoptsuite-3.1.0/zimpl-3.3.2'
-> generating library lib/libzimpl-3.3.2.linux.arm.gnu.opt.a
ar: crs: No such file or directory
make[2]: *** [lib/libzimpl-3.3.2.linux.arm.gnu.opt.a] Error 1
make[2]: Leaving directory `mypath/scipoptsuite-3.1.0/zimpl-3.3.2'
make[1]: *** [mypath/scipoptsuite-3.1.0/zimpl-3.3.2/lib/libzimpl.linux.arm.gnu.opt.a] Error 2
make[1]: Leaving directory `mypath/scipoptsuite-3.1.0'
make: *** [scipbinary] Error 2
I would particularly like to bring your attention to the following line within that segment of code:
ar: crs: No such file or directory
I am not really sure what the 'crs' aspect of that line is referring to, or even why any error is generated at all. Any help on this matter would be greatly appreciated. I am truly stumped at this point.
Change :
AR = ar cr
ARFLAGS =
To :
ARFLAGS += cs
And :
$(AR) $# $(LIBXXX) $(ARFLAGS)
To :
$(AR) $(ARFLAGS) $# $(LIBXXX)
ar is to be invoked like this (man ar(1)):
ar [--plugin name] [-X32_64] [-]p[mod [relpos] [count]] [--target bfdname] archive [member...]
So its flags can't be at the end of the command line if not marked as such, like -crs.
Also, make already define $(AR) and $(ARFLAGS) for you, there is no need for you to specify it again.
$ make -p | grep "^AR"
AR = ar
ARFLAGS = rv
Related
Automate the compilation of auto-generated C files with regular C files
We have developed a program "cperformer" that is able to generate a C file from a text file (to keep it simple).
It is a kind of "meta-compiler" that generates C file as output. Thus, we would like to improve the usage of this "C generator" by automating the generation of each C file as a first step of a makefile, and then compile and link together all of these generated C files with other C files already present with GCC in the same makefile.
Makefile 1
C_GEN :=./cperformer -n
CC :=gcc
CFLAGS :=-I.
#List all .c files generated from .text files
AUTO_SRCS = $(wildcard *.text)
AUTO_OBJS_C := $(patsubst %.text,%_alg.c,$(AUTO_SRCS))
$(info *INFO* Text files = $(AUTO_SRCS))
#List all .c files to compile (auto-generated or not)
SRCS = $(AUTO_OBJS_C)
SRCS += $(wildcard *.c)
OBJS := $(patsubst %.c,%.o,$(SRCS))
$(info *INFO* C files = $(SRCS))
# Main target rule
target : $(OBJS)
$(CC) -o $# $(OBJS) $(CFLAGS)
# Pre-compilation step (some C files generation)
prelim $(AUTO_OBJS_C): $(AUTO_SRCS)
$(C_GEN) $<
# Pre-compilation step (object files generation)
%.o: %.c
$(CC) -c -o $# $< $(CFLAGS)
all: prelim target
clean :
rm -f TARGET $(OBJS) *_alg*
Error 1
$ make all
*INFO* Text files = file3.text file2.text file1.text
*INFO* C files = file3_alg.c file2_alg.c file1_alg.c linked_list.c main.c
./cperformer -n file3.text
Compiling: file3.text ...
No error.
Done.
gcc -c -o file3_alg.o file3_alg.c -I.
./cperformer -n file3.text
Compiling: file3.text ...
No error.
Done.
gcc -c -o file2_alg.o file2_alg.c -I.
gcc: error: file2_alg.c: No such file or directory
gcc: fatal error: no input files
compilation terminated.
make: *** [Makefile:29: file2_alg.o] Error 1
It fails because the "cperformer" program is asked to generate the same C file each time "file3.c" so GCC don't find "file2.c" as expected and it aborts the compilation.
Makefile 2
Replace the C generative rule of the above makefile with the use of "%" :
# Pre-compilation step (some C files generation)
%.c: %.text
$(C_GEN) $<
Error 2
make: *** No rule to make target 'file3_alg.o', needed by 'target'. Stop.
Nothing compiles here.
Makefile 3
The dirty fix
batch_c_generation :
#$(foreach TXT_FILE, $(AUTO_SRCS), $(C_GEN) $(TXT_FILE);)
This is kind of working but remains very dirty because it re-generates all C files at each build and some duplication errors appear when it is not properly cleared between each make.
How can I fix the makefile ?
You were close -- simply fix your pattern rule to look like this:
%_alg.c : %.text
$(C_GEN) $<
As #tripleee mentioned, the reason your makefile1 rule failed was that it expands to something like:
file2_alg.c file1_alg.c: file2.text file1.text
$(CGEN) $<
In this case $< expands to the first dependency which will always be file2.text...
In your makefile2 example, you used %.c instead of %_alg.c (and hence there's no rule to build file2_alg.c, and therefore no rule to build file2_alg.o)
CC := cc
NAME := minishell
SRCS = ./Srcs/xsh.c
DIR = .build
OBJS := $(SRCS:%.c=$(DIR)%.o)
OBJS := $(addprefix $(DIR), $(OBJS))
$(DIR)/%.o : %.c
$(CC) -c -o $# $<
$(NAME) : $(OBJS) | $(DIR)
$(CC) -o $# $^
$(DIR):
mkdir -p $(#)
all : $(NAME)
I am trying to store all .o files in the build directory
Makefile:12: warning: overriding commands for target .build
Makefile:8: warning: ignoring old commands for target .build
make: *** No rule to make target %.c, needed by .build. Stop
Your line numbers are off by one which makes these errors hard to understand. Please be sure to include the exact makefile and errors so that they match up.
However, I assume that line #8 is:
$(DIR)/%.o : %.c
and line #12 is:
$(DIR):
The only way that this could give that error is if your DIR variable ended in spaces:
DIR = .build
^-space here
Makefiles preserve ending spaces on variables so be sure you don't do that.
Note if you had a newer version of GNU make it would warn about this:
Makefile:8: *** mixed implicit and normal rules: deprecated syntax
I guess that's still not super-helpful but it's something! :)
I am trying to compile all the files with a .c extension into an object folder and then create an executable. However, the Makefile I am using is not registering the source files at all. Instead it is going ahead and calling the command to create the executable with object files that do not exist.
Here is the Makefile:
CC = clang
SOURCE_DIR = src
OBJECT_DIR = objects
EXECUTABLE = main
SOURCES = $(wildcard $(SOURCE_DIR)/*.c)
OBJECTS = $(patsubst $(SOURCE_DIR)/%.c, $(OBJECT_DIR)/%.o, $(SOURCES))
all: $(OBJECTS)
$(CC) $^ -o $(EXECUTABLE)
clean:
rm objects/*.o main
$(OBJECT_DIR)/%.o: $(SOURCE_DIR)/%.c
$(CC) -c $< -o $#
.PHONY: all $(OBJECTS)
And here is the output:
me#hostname:~/parent_dir$ make
clang objects/main.o objects/test.o -o main
clang: error: no such file or directory: 'objects/main.o'
clang: error: no such file or directory: 'objects/test.o'
clang: error: no input files
make: *** [Makefile:11: all] Error 1
And here is the file structure:
parent_dir:
\ objects (empty):
\ src:
- main.c
- test.c
- Makefile
Replace:
.PHONY: all $(OBJECTS)
with:
.PHONY: all
The object files are not phony targets
and telling make they are phony tells it that no such files have to exist.
I have written a Makefile to generate a kernel image from both ASM and C sources however it fails to compile the C sources. I think the error is in using two object lists one for ASM and one for C. If there are other issues with the file please feel free to tell me.
Terminal Output
arm-none-eabi-as -I source/ source/maths.s -o build/maths.o
arm-none-eabi-as -I source/ source/tags.s -o build/tags.o
make: *** No rule to make target 'build/firstCFile.o', needed by 'build/output.elf'. Stop.
Makefile
# The toolchain to use. arm-none-eabi works, but there does exist
# arm-bcm2708-linux-gnueabi.
ARMGNU ?= arm-none-eabi
# The intermediate directory for compiled object files.
BUILD = build/
# The directory in which source files are stored.
SOURCE = source/
# The name of the output file to generate.
TARGET = bin/kernel.img
# The name of the assembler listing file to generate.
LIST = bin/kernel.list
# The name of the map file to generate.
MAP = bin/kernel.map
# The name of the linker script to use.
LINKER = kernel.ld
# The names of libraries to use.
LIBRARIES := csud
# The names of all object files that must be generated. Deduced from the
# assembly code files in source.
OBJECTS := $(patsubst $(SOURCE)%.s,$(BUILD)%.o,$(wildcard $(SOURCE)*.s))
OBJECTS2 := $(patsubst $(SOURCE)%.c,$(BUILD)%.o,$(wildcard $(SOURCE)*.c))
# Rule to make everything.
all: $(TARGET) $(LIST)
# Rule to remake everything. Does not include clean.
rebuild: all
# Rule to make the listing file.
$(LIST) : $(BUILD)output.elf
$(ARMGNU)-objdump -d $(BUILD)output.elf > $(LIST)
# Rule to make the image file.
$(TARGET) : $(BUILD)output.elf
$(ARMGNU)-objcopy $(BUILD)output.elf -O binary $(TARGET)
# Rule to make the elf file.
$(BUILD)output.elf : $(OBJECTS) $(OBJECTS2) $(LINKER)
$(ARMGNU)-ld --no-undefined $(OBJECTS) $(OBJECTS2) -L. $(patsubst %,-l %,$(LIBRARIES)) -Map $(MAP) -o $(BUILD)output.elf -T $(LINKER)
# Rule to make the object files.
$(BUILD)%.o: $(SOURCE)%.s
$(ARMGNU)-as -I $(SOURCE) $< -o $#
$(BUILD):
mkdir $#
I think you need a rule to make from the c source:
$(BUILD)%.o : $(SOURCE)%.c
$(ARMGNU)-gcc -c -I $(SOURCE) $< -o $#
I'm new to Stack Overflow. I'm currently having a hard time solving a simple problem.
In my shell/ directory, I have:
CVS/
include/
Makefile
obj
src
My problem occurs when trying to direct object files to be built in obj, but when I run make with the following code:
# Beginning of Makefile
OBJS = obj/shutil.o obj/parser.o obj/sshell.o
HEADER_FILES = include/shell.h include/parser.h
EXECUTABLE = simpleshell
CFLAGS = -Wall
CC = gcc
# End of configuration options
#What needs to be built to make all files and dependencies
all: $(EXECUTABLE)
#Create the main executable
$(EXECUTABLE): $(OBJS)
$(CC) -o $(EXECUTABLE) $(OBJS)
#Recursively build object files
%.o: %.c
$(CC) $(CFLAGS) -c -o $# $<
#Define dependencies for objects based on header files
#We are overly conservative here, parser.o should depend on parser.h only
$(OBJS) : $(HEADER_FILES)
clean:
-rm -f $(EXECUTABLE) obj/*.o
run: $(EXECUTABLE)
./$(EXECUTABLE)
tarball:
-rm -f $(EXECUTABLE) obj/*.o
(cd .. ; tar czf Kevin_Fairchild_a3.tar.z shell )
# End of Makefile
I get this error:
gcc -o simpleshell obj/shutil.o obj/parser.o obj/sshell.o
gcc: obj/shutil.o: No such file or directory
gcc: obj/parser.o: No such file or directory
gcc: obj/sshell.o: No such file or directory
gcc: no input files
make: *** [simpleshell] Error 1
What simple piece am I missing? I will continue to research and learn more about Makefiles
The trouble is that the pattern rule
%.o: %.c
...
doesn't actually match what you're trying to do. The source file is actually src/shutil.c, so this rule doesn't fit. All Make sees is this rule:
$(OBJS) : $(HEADER_FILES)
There are no commands, so Make concludes that no action is necessary. It then proceeds with the rule for simpleshell, which fails because the objects aren't there.
Try this:
obj/%.o: src/%.c
$(CC) $(CFLAGS) -c -o $# $<
There are more sophisticated variations, once this much is working.
after adding that simple modification, which I originally attempted before posting here, i.e.
obj/%.o: src/%.c
I recieved this error, so originally I though it was something else.
gcc -Wall -c -o obj/shutil.o
src/shutil.c
src/shutil.c:14:19: error: shell.h: No such file or directory
src/shutil.c: In function ‘signal_c_init’:
src/shutil.c:72: error: ‘waitchildren’ undeclared (first use in this function)
src/shutil.c:72: error: (Each undeclared identifier is reported only once
src/shutil.c:72: error: for each function it appears in.)
src/shutil.c: In function ‘checkbackground’:
src/shutil.c:90: warning: implicit declaration of function ‘striptrailingchar’
src/shutil.c: At top level:
src/shutil.c:101: warning: conflicting types for ‘striptrailingchar’
src/shutil.c:90: note: previous implicit declaration of ‘striptrailingchar’ was here
make: *** [obj/shutil.o] Error 1`
Thanks for the quick reply by the way!