I'm writing a custom kernel module (let's call it mod1) that I would like to export functions for use in other modules (let's call those mod2, etc...). When compiling the other modules, I get warning messages about undefined symbols (functions in mod1). Though everything should work fine after loading, I like to compile without warnings. I read that I should add the path to mod1's Module.symvers to KBUILD_EXTRA_SYMBOLS However, I noticed that my Module.symvers file is empty. What am I doing wrong?
Here's a MWE of a module:
#include <linux/module.h>
MODULE_INFO(version, "0.1");
MODULE_AUTHOR("Me");
MODULE_LICENSE("GPL");
int foo(int x) {
return x;
}
EXPORT_SYMBOL_GPL(foo)
And a Makefile:
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
And me running make showing that Module.symvers is empty:
user#host:~/mwe$ make; [[ -s ./Module.symvers ]] || echo "File size is zero!"
make -C /lib/modules/3.13.0-30-generic/build M=/home/user/mwe modules
make[1]: Entering directory `/usr/src/linux-headers-3.13.0-30-generic'
Building modules, stage 2.
MODPOST 0 modules
make[1]: Leaving directory `/usr/src/linux-headers-3.13.0-30-generic'
File size is zero!
I'm not sure what I'm doing wrong and my search for answers has been fruitless thusfar.
Looks like the Makefile is incorrect. Where is the name of the file you want to compile ? Change test.o to whatever your filename.
Makefile:
obj-m += test.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Related
I want to build a basic main.c, that is actually a kernel module written in C. I have include header files that are in include/. I want to use GCC -I to make GCC search for the include headers in -Iinclude. However, GCC doesn't seem to understand that, and I have no clue how to debug it.
Tree:
main.c
include
file.h
main.c
#include "file.h"
...
Makefile:
EXTRA_CFLAGS += -Iinclude -Werror -Wall \
-Wno-missing-braces -Wno-error=unused-function
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
The error:
main.c: fatal error: file.h: No such file or directory
That's because make is not actually running in your directory, when it compiles things.
The -C option in this command:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
tells make to change it's current working directory to that path. Thus, include is no longer the include directory in your current directory.
You should write it like this:
EXTRA_CFLAGS += -I'$M/include' -Werror -Wall \
-Wno-missing-braces -Wno-error=unused-function
all:
$(MAKE) -C "/lib/modules/$$(uname -r)/build" M='$(CURDIR)' modules
clean:
$(MAKE) -C "/lib/modules/$$(uname -r)/build" M='$(CURDIR)' clean
You should always use $(MAKE), and never make, when running a sub-make. And using make's shell function is not really needed since a recipe is already running in a shell. And, PWD is just inherited from the calling shell and might be inaccurate.
How can I display the absolute file path of ../linux/init.h that the linker deemed resolvable? IE, ! found init.h # /foo/bar/linux/init.h
I tried make VERBOSE=1, it didn't seem to do anything. Do I need to somehow pass a verbose linker argument to make?
#include <linux/init.h>
static int hello_init(void)
{
printk(KERN_ALERT "Hello, world\n");
return 0;
}
[/home/user/dev/kernel-sandbox/Makefile]
obj-m += lkm.o
all:
sudo make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
sudo make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
I am learning Linux kernel module programming. I am using Beaglebone black for that. I have made simple 'Hello World' application and makefile. I have checked my makefile it's proper. But when I command 'make', it gives me following error:
root#beaglebone:/home/sonu# make
make: Warning: File `Makefile' has modification time 2.2e+02 s in the future
make -C /lib/modules/3.8.13-bone70/build M=/home/sonu modules
make: *** /lib/modules/3.8.13-bone70/build: No such file or directory. Stop.
make: *** [all] Error 2
Though I referred some websites. But, all they are asking me to install packages. As I am a newbie. I don't even know how to configure and start internet connection on Beaglebone using ethernet. Please help me I am stuck. Thanks in advance.
Code is:
#include<linux/module.h>
#include<linux/kernel.h>
#include<linux/init.h>
static int __init hello(void)
{
printk(KERN_INFO "Hello World!");
return 0;
}
static void __exit hello_cleanup(void)
{
printk(KERN_INFO "Bye");
}
module_init(hello);
module_exit(hello_cleanup);
Makefile is:
obj-m+=Hello.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
$(CC) Hello.c -o test
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
rm test
It appears that you're trying to build your module for a kernel version that you haven't installed the headers for.
Instead of calling uname directly in your rules, it's helpful to put that into a variable you can override:
obj-m+=Hello.o
KSRC := /lib/modules/$(shell uname -r)/build
all:
make -C $(KSRC) M=$(PWD) modules
$(CC) Hello.c -o test
clean:
make -C $(KSRC) M=$(PWD) clean
rm test
Now, you can override with the actual location of your kernel headers:
make KSRC=/usr/src/linux-headers-4.9.2 all
You can simplify the Makefile further with a catch-all rule:
obj-m+=Hello.o
KSRC := /lib/modules/$(shell uname -r)/build
all: modules
$(CC) Hello.c -o test
%:
make -C $(KSRC) M=$(PWD) $#
clean::
make -C $(KSRC) M=$(PWD) clean
$(RM) test
I'm trying to write a simple Makefile for a module, I've got all the right components, I've replaced all the spaces in the beginning of lines with tabs.
Makefile:1: *** missing separator (did you mean TAB instead of 8 spaces?). Stop.
This is my Makefile
obj-m += hello-1.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
I am trying to compile a Linux kernel module using the standard example Makefile specified in the Linux Kernel Module Programming Guide. If the Makefile is called Makefile, then everything works. If I rename the Makefile to Makefile.hello or something else, then it fails as it cannot find the path Makefile. I was wondering if there is a command or set of flags I can add to my Makefile to make this function properly. I need to rename the Makefile as I am calling it from CMake. Cmake creates its own Makefiles and will commonly overwrite what I already have.
I replaced my kernel module code with the hello world example and replicated the problem. I know its the makefile.
hello world example hello.c
/*
* hello−1.c − The simplest kernel module.
*/
#include <linux/module.h> /* Needed by all modules */
#include <linux/kernel.h> /* Needed for KERN_INFO */
int init_module(void)
{
printk(KERN_INFO "Hello world 1.\n");
/*
* A non 0 return means init_module failed; module can't be loaded.
*/
return 0;
}
void cleanup_module(void)
{
printk(KERN_INFO "Goodbye world 1.\n");
}
Makefile
obj-m += hello.o
ifeq (,$(KDIR))
KDIR := /lib/modules/$(shell uname -r)/build
endif
PWD := $(shell pwd)
all:
$(MAKE) -C $(KDIR) M=$(PWD) $(KCONFIG) modules
clean:
$(MAKE) -C $(KDIR) M=$(PWD) clean
If makefile is called Makefile. (Successfully builds)
$> make -f Makefile
make -C /lib/modules/4.4.0-21-generic/build M=/home/msmith/Desktop/kernel-test modules
make[1]: Entering directory '/usr/src/linux-headers-4.4.0-21-generic'
CC [M] /home/msmith/Desktop/kernel-test/hello.o
Building modules, stage 2.
MODPOST 1 modules
CC /home/msmith/Desktop/kernel-test/hello.mod.o
LD [M] /home/msmith/Desktop/kernel-test/hello.ko
make[1]: Leaving directory '/usr/src/linux-headers-4.4.0-21-generic'
Make output if makefile is called Makefile.hello (Fails to build)
$> make -f Makefile.hello
make -C /lib/modules/4.4.0-21-generic/build M=/home/msmith/Desktop/kernel-test modules
make[1]: Entering directory '/usr/src/linux-headers-4.4.0-21-generic'
scripts/Makefile.build:44: /home/msmith/Desktop/kernel-test/Makefile: No such file or directory
make[2]: *** No rule to make target '/home/msmith/Desktop/kernel-test/Makefile'. Stop.
Makefile:1396: recipe for target '_module_/home/msmith/Desktop/kernel-test' failed
make[1]: *** [_module_/home/msmith/Desktop/kernel-test] Error 2
make[1]: Leaving directory '/usr/src/linux-headers-4.4.0-21-generic'
Makefile.hello:10: recipe for target 'all' failed
make: *** [all] Error 2
I tried adding the -f to the internal MAKE parameters, however that just caused more issues.
Move all Kbuild-related logic into the file Kbuild. Kernel's build system checks file with this name first, so it won't look into Makefile, created by CMake. This feature is documented in Documentation/kbuild/makefiles.txt.
I use exactly this approach in my CMake projects, related with Linux kernel.
Open script/Makefile.build into kernel tree:
41 # The filename Kbuild has precedence over Makefile
42 kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
43 kbuild-file := $(if $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Kbuild,$(kbuild-dir)/Makefile)
44 include $(kbuild-file)
This part of code (43-44) include Makefile with name 'Makefile'.
The default Makefile. Name = Makefile ... and Makefile-hello, or Makefile.hello.
obj-m := hello.o
KDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
clean:
$(MAKE) -C $(KDIR) M=$(PWD) clean
$ make : OK
$ make -f Makefile-hello OK
$ make -f Makefile.hello Also OK.
Your Makefile : $ make -f Makefile.msmith OK, no errors.