So when I try to run a compiled C program on my school's "hercules" server, it runs as I would normally expect it to. However, I've got an assignment that requires the use of forks, and running programs that fork on that server is forbidden, instead, I am to run them by remotely connecting to one of several Linux machines and running it there, from command line
However, any attempt to do so gives me this error:
shell2: Exec format error. Binary file not executable.
Altogether, my command prompt looks like this:
a049403[8]% shell2
shell2: Exec format error. Binary file not executable.
I've got the shell2 file in the working directory, when I type "ls" it shows it with the * character indicating it is notionally an executable. I've tried setting its permissions to 777. It produces the same error for other C programs which I have been working with and running, and "hercules" can run the exact same file without any difficulties or complaints. My make file for this particular program looks like this:
all: shell2
Basics.o: Basics.c Basics.h
cc -c Basics.c
doublinked.o: doublelinked.c doublelinked.h
cc -c doublelinked.c
main.o: main.c Basics.h doublelinked.h
cc -c main.c
shell2: main.o Basics.o doublelinked.o
cc main.o Basics.o doublelinked.o -o shell2
clean:
rm -f *o shell2
...and if I re-run the makefile it seems to build the program with no difficulties.
So, and reason an environment that can compile C programs would be unable to run them? Any likely workarounds?
First, your Makefile is not very good. See this example and this one to improve it. Always pass -Wall -g flags (to get all warnings and debug info) to gcc when compiling some home work.
Then, a possible explanation of why your binary program don't run on the target machine could be libc version mismatch. Or perhaps one system is 32 bits and the other is 64 bits. Use file shell2 to find out.
I suggest to make clean then recompile again (e.g. with make all) on the target machine.
Learn how to use the gdb debugger.
If you're running a program compiled on a different (incompatible) architecture, you'll almost certainly run into troubles.
It's a little unclear from the question whether you're transferring and attempting to run the executable, or trying to build the executable from scratch on the new machine. It's also unclear whether your make (if you're running it on the new machine) is completely rebuilding everything.
However, given the "Exec format error", it's a safe bet that the former case is the one you're encountering, trying to run an incompatible executable file.
So, here's my advice. Transfer everything to the new machine and execute:
make clean all
to ensure everything is being rebuilt.
Related
The program is to run a c program to parse a xml file in windows Gcc mingw.
but on compilation i get xml2-config not found ,--libs unrecognized commands, --cflags unrecognized commands.
gcc
i have added libxml files "libxml libxslt iconv" to the environmental path.
When you write a program that uses a third-party library like libxml, typically you have two problems:
You need to tell the compiler where the library's header files are installed, so that when your code says things like #include <xml.h> the compiler will be able to find them.
You need to tell the linker where the library itself is installed.
If you don't manage to do step 1 correctly, you typically get an error like "error: 'xml.h' file not found".
If you don't manage to do step 2 correctly, you typically get errors like "Undefined symbol: _xmlparse" or "library not found for -llibxml". ("Undefined symbol" means the compiler didn't even know to look for the library, so it complains that there are no definitions for the functions that would have been found in it. "library not found for -llibxml" means you told the compiler which library to look for, but it couldn't find it.)
On C compilers under Unix, anyway, you tell the compiler where to look for header files using the -I flag, like this:
cc -Idirectory_where_extra_header_files_are -c test.c
You tell the compiler/linker to load an additional library using the -l flag:
cc test.o -llibxml
You tell the compiler/linker where to find that additional library using the -L flag:
cc test.o -Ldirectory_where_extra_library_files_are -llibxml
But this can be a nuisance. Many third-party libraries come with "config" programs which are supposed to help you with this. An invocation like
xml-config --cflags
prints the string
-Idirectory_where_the_libxml_header_files_are
so you know what to add to the cc line to fix problem 1. And the an invocation like
xml-config --libs
prints the string
-Ldirectory_where_the_libxml_libraries_are -llibxml
so you know what to add to the cc line to fix problem 2.
And then, finally, this tool is intended to be used a special mechanism of the Unix shell, the backquote, which lets you take the output of one command and insert it into another command line:
cc `xml-config --cflags --libs` test.c
This literally runs the xml-config command, collects its output (that is, whatever xml-config prints out), and inserts that input into the command line, just as if you'd typed it, and then finally runs the cc command with those additional arguments. It's a handy mechanism, but if you're using Windows you may not be able to use it.
So if you're on a Unix-like system and if the xml-config program is installed where the shell can find it and if the header files and libraries are installed where xml-config thinks they are, then using xml-config can be very convenient. But if any of these things is not true, the whole mechanism breaks down, and you may have to do things "by hand".
Doing things "by hand" isn't impossible, and it isn't even particularly difficult. It's how we always did things back before this kind of "config" tool helper mechanism was invented. As discussed above, just use -I to tell the compiler where the header files are when you compile:
cc -Idirectory_where_the_libxml_header_files_are -c test.c
Use -L and -l to tell it where the library is:
cc test.o -Ldirectory_where_the_libxml_libraries_are -llibxml
For my WINAPI projects, I am using atom IDE with c programming, I could compile my code from cmd prompt without a problem until I have started using .rc files. but now that I am using rc files before compiling my program I need to run these commands on the cmd prompt.
gcc -c jake.c
gcc -o jake jake.o -mwindows
windres -o jakerc.o jakerc.rc
gcc -o jake jake.o jakerc.o -mwindows
typing them all again and again to see if my program works correctly each time is really tedious. (Also please do not tell me to use IDEs like DEV c++ or Visual Studio because I don't like them as much as I like atom.)
so I have came up with this solution. I have made an extra file called compile.c which inside it looks like this.
#include <stdio.h>
#include <stdlib.h>
int main() {
system("C:\\Users\\hashtag\\Desktop\\rawsock\\kokul gcc -c jake.c");
system("C:\\Users\\hashtag\\Desktop\\rawsock\\kokul gcc -o jake jake.o -mwindows");
system("C:\\Users\\hashtag\\Desktop\\rawsock\\kokul windres -o jakerc.o jakerc.rc");
system("C:\\Users\\hashtag\\Desktop\\rawsock\\kokul gcc -o jake jake.o jakerc.o -mwindows");
return 0;
}
When I compile and run this program I get this error:
'C:\\Users\\hashtag\\Desktop\\rawsock\\kokul' is not recognized as an internal or external command,
operable program or batch file.
How do I get rid of this error, and how do I automatically compile my files when I run compile.exe?
as mentioned in my comment, i'd recommend using a batchfile and not a compiled c program for this.
Example:
#ECHO off
SET workingDirectory=%~dp0
SET fileName=%1
echo using %workingDirectory% as working directory
gcc -c %fileName%.c
gcc -o %fileName% %fileName%.o -mwindows
windres -o %fileName%rc.o %fileName%rc.rc
gcc -o %fileName% %fileName%.o %fileName%rc.o -mwindows
you could run your desiered commands with nameofthebatchfile.bat jake
As long as kokul is a directory the command line
C:\\Users\\hashtag\\Desktop\\rawsock\\kokul gcc -c jake.c
Doesn't make sense.
You can combine multiple commands. If you want to change into the directory kokul and start the compile this will work
CD C:\\Users\\hashtag\\Desktop\\rawsock\\kokul & gcc -c jake.c
But anyhow writing a batch file is much easier:
You can do it with two lines
windres -o jakerc.o jakerc.rc
gcc -o jake jake.c jakerc.o -mwindows
Save them to file "mj.bat", then run form command prompt by typing "mj".
When your project grows beyond two or thre files, you should use makefile
GCC and Make Compiling, Linking and Building C/C++ Applications
Check also atom-shell-commands or run-command package for Atom. You can run this directly form editor.
If you're working with command-line tools, this task just seems to cry out for a Makefile. Not only will make automate the necessary actions, it will try to work out from the file timestamps which actions actually need to be carried out. If you haven't changed a C source file, for example, you don't need to recompile it. The effectiveness of make, or similar, will increase enormously as your applications get larger and have more complicated dependencies between components.
You can do some of this stuff with simple batch files but, ideally, the batch file needs to stop when any of the steps encounters an error. There's no point carrying on a long build process that is doomed to fail, and finding the relevant error message in pages of irrelevant output can be a chore. This is another thing that make just does right.
It can take a while to get on top of Makefiles, with their arcane syntax. However, the effort will be rewarded many times over in the longer term.
I have a makefile which builds my .C project, and produces an executable file. I know this can then be run from using the command ./(NAME) from the terminal.
My question is this - is it possible to actually build AND run within the makefile, so that i would just be able to type 'make' in the terminal, and the program would be built and run, all from this one file & command? (without the need of manually running the executable file).
Thanks :)
No idea what is you makefile, but you could do something like that:
PROGARGS=
.PHONY:all run
all:prog
#...
run:all
./prog $(PROGARGS)
Yes, it can.
For example:
TARGET=hoge
CC=gcc
.PHONY: compileandrun
compileandrun: $(TARGET)
./$(TARGET)
$(TARGET): $(TARGET).c
$(CC) -o $(TARGET) $(TARGET).c
If you have this Makefile and the source code hoge.c in your writable current directory, the program will be compiled and run with make command.
The other answers are good; however, you can use this other variant (a quick-and-dirty solution).
Suppose your makefile has this line to build your program:
NAME:
gcc source.c -o NAME
You can add your running command directly below:
NAME:
gcc source.c -o NAME
./NAME
This does the same as && concatenation: it runs the first command, and if successful, the second command too.
As long as you sequence your makefile dependencies correctly, there is nothing stopping you from running you C program from the makefile. That said, most people would expect a makefile to just build the file and not also run it at the same time.
I would recommend just writing the make command and the run command in a single line in the command line. This way you only need to press enter once but don't need to do anything fancy in the makefile itself. If your shell supports history completion, the next time you want to build and run again you only need to press "UP" and "ENTER"...
make && ./NAME
If you really want to put everything inside the makefile, I would recommend creating a separate "run" target in your makefile to reduce the chance of confusion, like in jdarthenay's answer.
Hello i am new to ubuntu. I want to run a c program in ubuntu.On the terminal i typed "make ex1.c" (my file name is ex1) and the after pressing enter button , terminal is telling me that
"no rule to make target 'ex1.c'. stop " .
How can i proceed?
Try this
$ gcc -Wall ex1.c -o ex1
$ ./ex1
-Wall makes all the warnings explicit. It is considered to be a good practice to always enable -Wall option. -o ex1 specifies the output executable to be ex1.
GCC is the default C compiler on Ubuntu. An elegant introduction to gcc can be read in here.
make needs no rules to make a simple C file, all it needs is the basename, without the .c extension:
make ex1
./ex1
I advise you to start using the gcc command though. You will have more control on how stuff is compiled and along the way, you'll learn how building an application works. make will start making sense if you have a larger project with many (inter dependent) files.
More (a lot!) information here: http://gcc.gnu.org/onlinedocs/gcc-4.8.2/gcc/, or by typing man gcc in the terminal.
Best is to use GCC or you are getting error because you are attaching ".c".So don't put extension in make command.Try without putting extension like following:
make ex1
./ex1
Compile the following program
#include <stdio.h>
int main(void)
{
printf ("Hello from your first program!\n");
return 0;
}
a)-by using file of type Makefile
b)-the executable will be named Hello
"Please help to do an exercise. I know how to do it in CodeBlocks, but I don't know what Makefile is and how to write it in Linux. I compiled it using command "gcc filename.c" and subsequently "./a.out" but I still don't understand what the Makefile is. Is it a sort of shell script, an instruction? How would a Makefile for this task exactly look? Thanks in advance :) "
This is your simple make file for hello program.
CC = gcc
CFLAGS = -g
RM = rm -f
default: all
all: Hello
Hello: Hello.c
$(CC) $(CFLAGS) -o Hello Hello.c
clean veryclean:
$(RM) Hello
Suppose you have two makefiles in one directory named makefile.m1 and makefile.m2 and if you want build both make file then please use following commands
make -f makefile.m1
make -f makefile.m2
or use single Makefile that contains:
m1:
make -f makefile.m1
m2:
make -f makefile.m2
and use make m1 or make m2
Now lets clear your doubt about name of make file must not require Makefile
You can name makefile whatever you want. suppose i would like to give name myfirstmakefile.mk. To use it later you need to tell make what makefile you want. Use -f option for this:
make -f myfirstmakefile.mk
And again extantion .mk is also not manadatory you can use whatever you want but never forgot to use -f option.
so may this help make sense to you.
A makefile is a recipe for the make utility how to create some file (called a target) from some other files (called dependencies) using a set of commands run by the shell. A makefile typically looks like this:
target: dependency [...]
command1
command2
Try running man make for details.
Now for your task, really there is no need for a Makefile, since make has built-in rules that know how to compile a simple program. All you need to do is place your C source in a file named after the executable name (Hello) and with a .c extension, i.e. Hello.c.
Then a simple
$ make Hello
cc Hello.c -o Hello
does everything. If you want to use gcc instead of cc, you can run
$ rm Hello
$ make CC=gcc Hello
gcc Hello.c -o Hello
If you tell your instructor/teacher/prof that an empty makefile is all you need since you know the built-in rules do the right thing, you'll get some extra credit and maybe your instructor has learnt something new :-) If you are asked for a reference, you could quote the relevant parts of the make manual, or, do it like a pro, quote from the POSIX Standard for the make utility, section Default Rules.
before going for makefile you have to know what's it and why we need it
What is Makefile?
Makefile is a script written in a certain prescribed syntax which helps to build the target output (normally, one or more executables) from source files by compilation and linking. In simple words, makefile will compile your source code in simple & fast way.
Why we need Makefile?
=> Large projects can contain multiple source files which are dependent in one another or arranged in hierarchical manner for example, in order to compile file A, you have to first compile B; in order to compile B, you have to first compile C; and so on.
=> Make is a solution to these problems. It can be used to compile whole project in well arranged manner and generate your target according to your make rule(which we will discuss later) by entering single command that is make.
=> An important feature is that when a project is recompiled after a few changes, it will recompile only those files which are changed, and any other files that are dependent on it. This saves a lot of time.
=> For a large project, when a few changes are made to the source, manually recompiling the entire project each time is tedious, error-prone and time-consuming.
Here is nice link for it :How to write first makefile
A makefile is a recipe for computers with instructions how to perform certain tasks and with dependencies between those tasks.
In the simple form, it looks like so:
a.out: filename.c
gcc filename.c
Read: "To build a.out from filename.c, run the command gcc filename.c. If a.out is newer than filename.c, then don't do anything"
Note: The first character in the gcc line must be a tab.