VHDL read from RAM and store in array delay? - arrays

Question

I am currently doing a project in VHDL and since I am not an expert I am having some problems.
I'll try to clarify everything. So let's split in parts.
What I am trying to do is to write certain values in two different RAM memories and then reading from them and storing different values into an array which would be used by a different block to perform MAC filtering.
Here is the RAM code that I am using (is a modification of the code provided by Weijun Zhang) I don't know if I have to post the link here. If somebody needs it 'll post it
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
entity SRAM is
generic( width: integer:=32;
depth: integer:=1024;
addr: integer:=10);
port( clk: in std_logic;
enable: in std_logic;
read_en: in std_logic;
write_en: in std_logic;
read_addr: in std_logic_vector(addr-1 downto 0);
write_addr: in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0)
);
end SRAM;
--------------------------------------------------------------
architecture behav of SRAM is
-- use array to define the bunch of internal temporary signals
type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type:= ((others=> (others=>'0')));
begin
-- read_en Functional Section
process(clk, read_en)
begin
if (clk'event and clk='1') then
if enable='1' then
if read_en='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(read_addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- write_en Functional Section
process(clk, write_en)
begin
if (clk'event and clk='1') then
if enable='1' then
if write_en='1' then
tmp_ram(conv_integer(write_addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
This RAM code works fine, I can't attach images because I don't have enough reputation (this somehow sounds familiar to me...)
What I wanted to explain with the image, is that at the same moment that I set an address to read, the output value is the value contained in that address.
Now let´s move to the actual problem:
What I am trying to do is to create a block with two of these RAM memories. One of this RAM is used to store the values of the input to be filtered, and the other one is to store the values of the filter coefficients. So the execution would be something like this:
Write only input coefficient into its dedicated memory (address from 1 to 1024)
Write all the new coefficients into their memory (again address from 1 to 1024)
Read from both memories one coefficient and one input value (staring from address 1) and store them in two arrays (in this case array of 4 vectors)
Fill up the arrays (3 cycles more in step 3)
Once the array is full perform the filtering with 4 input values and 4 coefficients (still not implemented)
Start again point 3
I'll try to save all the space that I can removing several lines (initialization and port declaration)
library IEEE; -- declare the library
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library work;
use work.mypackage.all; -- use of mypackage to use arrays as inputs
entity MAC_1024 is
port( clk: in std_logic;
enable: in std_logic;
enable_MAC: in std_logic;
rst: in std_logic;
read_input_en: in std_logic;
write_input_en: in std_logic;
read_coeff_en: in std_logic;
write_coeff_en: in std_logic;
X: in std_logic_vector(31 downto 0);
W: in std_logic_vector(31 downto 0);
Yt: out std_logic_vector(31 downto 0);
Yn: out std_logic_vector(31 downto 0)
);
end MAC_1024;
Now declaration of two RAMs
input_RAM: SRAM generic map (width=> t_width, depth=> t_depth, addr=> t_addr)
port map (clk, enable, read_input_en, write_input_en,read_input_addr, write_input_addr, X, saved_input);
coeff_RAM: SRAM generic map (width=> t_width, depth=> t_depth, addr=> t_addr)
port map (clk, enable, read_coeff_en, write_coeff_en,read_coeff_addr, write_coeff_addr, W, saved_coeff);
Here comes the process (the constant one has the value "0000000001")
process (clk, write_input_en, write_coeff_en)
begin
if (clk'event and clk='1') then
if (write_coeff_en='1') then
write_coeff_addr <= cont2;
cont2 <= unsigned(cont2) + unsigned(one);
end if;
if (write_input_en='1') then
i:=0;
write_input_addr <= cont1;
cont1 <= unsigned(cont1) + unsigned(one);
end if;
if (read_input_en='1' and read_coeff_en='1') then
read_input_addr <= cont3;
read_coeff_addr <= cont4;
X_in(i) <= saved_input;
W_in(i) <= saved_coeff;
cont3 <= unsigned(cont3) + unsigned(one);
cont4 <= unsigned(cont4) + unsigned(one);
X_in(i) <= saved_input;
W_in(i) <= saved_coeff;
i:=i+1;
if(i=4) then
i:=0;
end if;
end if;
end if;
end process;
Yn <= X_in(0);
Yt <= saved_input;
As you can see I am using the variable i to start in 0 and be filling up the arrays X_in and W_in. When the value is 4 then the position to place in that array goes back to 0.
The outputs Y_n and Y_t are used to test the functionality. Y_n outputs the value stored in X_in[0] and Y_t the output value of the RAM of the coefficients
So let's say to keep it simple that I have a sequence of input values (X) that is 1,2,3,4....1024 and each of these values are stored in address 1,2,3,4....1024
I would expect to be placing the values in the array following the next sequence:
X_in [Z Z Z 1]
X_in [Z Z 2 1]
X_in [Z 3 2 1]
X_in [4 3 2 1]
X_in [4 3 2 5]
X_in [4 3 6 5]
...
(when read enable is active)
The output Y_n (which reads X_in[0]) would be 1 1 1 1 5 5 5 5 9 9 9 9...
and the output Y_t (which reads RAM output) would be 1 2 3 4 5 6 7 8 9 ...
but what I obtain instead is
Y_n Z Z Z Z 4 4 4 4 8 8 8 8....
Y_t 1 2 3 4 5 6 7 8 9 ... (which is expected)
It looks like a problem with the index i (if read output the value X_in[1] I obtain the values that would correspond to my expected X_in[0] ), but if it was that in the same moment that I obtain in Y_t the value 4 I should obtain the value 4 in Y_n but i still got the previous Z. (bold)
The same happens to the array W_in...
Frankly I am kind of lost, I dont know if there is a problem with i, with delay or with what.
I have tried to be clear but I can understand that is a problem rather complicated to explain
Thank you very much for the help
Update 1:
I don't want to reset the address counters because I want to write in sequential addresses from 1 to 1024. Since the address depth is 1024 is 10 bits i am adding to the address the constant one which is a constant with 10 bits ("0000000001"). Once "1111111111" is reached the next address would be "0000000000". The code right now is prepared for a 1024 FIR filter, later i would try to do more flexible. Also i just want to add one value of input values to the memory but 1024 new coefficients every filter cycle, so the counter for coefficient could be reset after writing operation, but i dont reset the counter for input values because i need to know where i will store this value.
Update 2: I have been reading that the data output appears some cycles after you set the address to read in RAM (normally one cycle). That would be a possible cause for my problem but then why is my RAM code working without any delay???

Answer 1

You shouldn't drive i in two other if statements. Try to Change to if...elseif. Maybe it's not a reason of your bug but it's a basic rule.