so I have finished a big C project in eclipse and I did this by right clicking my C project folder -> properties -> C/C++ Build -> Settings -> GCC C Compiler and putting the flags
-c -std=c99
And everything is passing when I build and run my program in ECLIPSE.
Now when I move my project over to linux version:
[ubuntu#ip-172-31-25-10:~/Desktop/Fall_2013/MIPSAssembler]$gcc --version
gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3
and run the following Makefile:
#
# Makefile to build the MIPS assembler
#
# DIRECTIONS: In the same folder that this folder is
# in type to the command line "Makefile"
CC = gcc
CFLAGS = -O -std=c99
OBJECTS = CUnit.o VariableVector.o preprocessor.o utilities.o parser.o assembler.o \
variableVectorTest.o preprocessorTest.o utilitiesTest.o parserTest.o assemblerTest.o
# Build for full program
assembler: $(OBJECTS)
$(CC) $(CFLAGS) -o assemble $(OBJECTS)
# Rules for components
CUnit.o: CUnit.c CUnit.h
$(CC) $(CFLAGS) -c CUnit.c
VariableVector.o: VariableVector.c VariableVector.h
$(CC) $(CFLAGS) -c VariableVector.c
preprocessor.o: preprocessor.c preprocessor.h
$(CC) $(CFLAGS) -c preprocessor.c
utilities.o: utilities.c utilities.h VariableVector.o
$(CC) $(CFLAGS) -c utilities.c
parser.o: parser.c parser.h utilities.o
$(CC) $(CFLAGS) -c parser.c
assembler.o: assembler.c assembler.h VariableVector.o
$(CC) $(CFLAGS) -c assembler.c
variableVectorTest.o: variableVectorTest.c variableVectorTest.h
$(CC) $(CFLAGS) -c variableVectorTest.c
preprocessorTest.o: preprocessorTest.c preprocessorTest.h CUnit.o
$(CC) $(CFLAGS) -c preprocessorTest.c
utilitiesTest.o: utilitiesTest.c utilitiesTest.h utilities.o
$(CC) $(CFLAGS) -c utilitiesTest.c
parserTest.o: parserTest.c parserTest.h VariableVector.o
$(CC) $(CFLAGS) -c parserTest.c
assemblerTest.o: assemblerTest.c assemblerTest.h
$(CC) $(CFLAGS) -c assemblerTest.c
clean:
rm -rf *.o
everything compiles but when I run my tests by typing
./assemble // I get some seg faults!!!
I was wondering why is my code working in ECLIPSE but not working in LINUX running gcc and how can I make it so that my eclipse compiling matches how I am compiling my files using gcc on linux? Thanks!
Related
I am new to c programming, and I am having a problem with making Makefile for it.
I did like
CC = gcc
CFLAGS = -fsanitize=address -g -Wall -Wvla
OUTPUT = prac
all: $(OUTPUT)
mymalloc.o: mymalloc.c mymalloc.h
$(CC) $(CFLAGS) -c $# mymalloc.c
%: %.c
$(CC) $(CFLAGS) -o $# mymalloc.o $^
and I try to make file with just typing "make"
But it keep says
gcc -fsanitize=address -g -Wall -Wvla -o prac mymalloc.o prac.c
clang: error: no such file or directory: 'mymalloc.o'
make: *** [prac] Error 1
whenever I try to make it , did I do something wrong?
Thank you.
Edit)
I got it right with using this!
CC = gcc
CFLAGS = -fsanitize=address -g -Wall -Wvla
DEPS = mymalloc.h
OBJS = prac.o mymalloc.o
%.o: %.c $(DEPS)
$(CC) $(CFLAGS) -c -o $# $<
prac: $(OBJS)
$(CC) $(CFLAGS) -o $# $^
You need to make the executable dependent on mymalloc.o:
%: %.c mymalloc.o
$(CC) $(CFLAGS) -o $# mymalloc.o $^
The dependency tells make that it needs to execute the rule for creating mymalloc.o.
Also your rule for making mymalloc.o is wrong. You need -o before $#:
mymalloc.o: mymalloc.c mymalloc.h
$(CC) $(CFLAGS) -c -o $# mymalloc.c
Otherwise it's trying to use the output file as one of the input files.
I want to compile a C program from GitHub on Windows 7 and get an error that a file is not found. I have installed MinGW Make and its dependancies. I think maybe this program is only intended to run on Linux.
The Console output:
E:\work-c\iso2opl-clone\iso2opl>make
gcc -std=gnu99 -pedantic -usr\include -usr\local\inc
lude -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SOURCE -c isofs.c -o isofs.o
process_begin: CreateProcess(NULL, gcc -std=gnu99 -pedantic -F:\programs\mingw\i
nclude -F:\programs\mingw\local\include -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SO
URCE -c isofs.c -o isofs.o, ...) failed.
make (e=2): Le fichier spécifié est introuvable.
make: *** [isofs.o] Erreur 2
the makefile:
CC = gcc
CFLAGS = -std=gnu99 -pedantic -I/usr/include -I/usr/local/include -D_FILE_OFFSET_BITS=64 -D_LARGEFILE64_SOURCE
#CFLAGS += -DDEBUG
ifeq ($(_WIN32),1)
CFLAGS += -D_WIN32
endif
OBJS = isofs.o \
iso2opl.o
all: $(TARGET)
rm-elf:
-rm -f $(TARGET) $(OBJS)
$(TARGET): $(OBJS)
$(CC) $(OBJS) -o $(TARGET) $(LIBS)
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
%.o: %.cpp
$(CC) $(CFLAGS) -c $< -o $#
clean:
rm -r $(OBJS) $(TARGET)
I don't know maybe the paths are wrongs.
Best Regards
Try to run the make in the MSYS2 shell (https://www.msys2.org/). I was able to build the sources from https://github.com/arcadenea/iso2opl without issue.
I'm trying to change my makefile to redirect the .o to a lib folder (and have the .c in a src folder). I would also like the executables to be at the same level as the makefile.
As for the .h, I have no idea where to put it!
CC = gcc
CFLAGS = -std=c11 -Wpedantic -Wall -Wextra -Wconversion -Werror -fPIC -pthread -D_XOPEN_SOURCE=500 -fstack-protector
LDLIBS = -lrt
RM = rm -f
ARFLAGS = rs
all: server client info_proc info_user
server: server.o header.o
$(CC) $(CFLAGS) -o $# $^ $(LDLIBS)
server.o: server.c header.h
gcc -c server.c
client: client.o header.o
$(CC) $(CFLAGS) -o $# $^ $(LDLIBS)
client.o: client.c header.h
header.o: header.c header.h
gcc -c header.c
info_proc: info_proc.o
info_proc.o: info_proc.c
gcc -c info_proc.c
info_user: info_user.o
info_user.o: info_user.c
gcc -c info_user.c
rmpipe:
$(RM) question_pipe
clean:
$(RM) server client info_proc info_user question_pipe *.o *~$
You could do something like this:
all: main
main: lib/a.o lib/b.o lib/main.o
$(CC) $(CFLAGS) -o $# $^
lib/a.o: a.c
$(CC) $(CFLAGS) -c -o $# $<
lib/b.o: b.c
$(CC) $(CFLAGS) -c -o $# $<
lib/main.o: main.c
$(CC) $(CFLAGS) -c -o $# $<
Or instead of writing your own Makefile you could use one of these build
tools:
GNU Autotools
Cmake
SCons
which on the long run are much easier to maintain than a self-written
Makefile.
I am trying to have the compiled obj files in two different folder
dobjects: where the objects have the debug symbol (gcc with -g option)
sobjects: where the objects are compiled without the debug symbols.
Source files are the same,
I have the following makefile.
CC = gcc
CFLAGS = -Wall
OBJS = a.o b.o
SRCS = a.c b.c
SOBJS_DIR = sobjects
DOBJS_DIR = dobjects
SOBJS = $(addprefix $(SOBJS_DIR)/, $(OBJS))
DOBJS = $(addprefix $(DOBJS_DIR)/, $(OBJS))
all: release debug
release: $(SOBJS)
debug: $(DOBJS)
$(DOBJS_DIR)/%.o: CFLAGS += -g
$(DOBJS_DIR)/%.o $(SOBJS_DIR)/%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
clean:
rm dobjects/*
rm sobjects/*
But every time I try "make" only one target is made.
$ make
gcc -Wall -c a.c -o sobjects/a.o
gcc -Wall -c b.c -o sobjects/b.o
$ make
gcc -Wall -g -c a.c -o dobjects/a.o
gcc -Wall -g -c b.c -o dobjects/b.o
any help would be greatly appreciated
This rule does not do what you think it does:
$(DOBJS_DIR)/%.o $(SOBJS_DIR)/%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
Pattern rules with multiple targets tell make that one single invocation of the recipe will build BOTH targets. So when make runs that rule to build $(DOBJS_DIR)/a.o, make believes that $(SOBJS_DIR)/a.o was also built, so it doesn't try to run the rule to build it. But your rule doesn't actually build it, so when you run make a second time it sees that object file is missing and runs the above rule again, to build the missing one.
You have to write this as two different rules:
$(DOBJS_DIR)/%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
$(SOBJS_DIR)/%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
I am making my first Makefile for a simple shell system. I need to make library files but for some reason the library section is not working out. In the error message it says the library files do no exist (obviously).
Am I missing something obvious that could fix this? Also, is there any other way I can make this Makefile more efficient?
# Beginning of Makefile
OBJS = obj/shutil.o obj/parser.o obj/sshell.o obj/history.o obj/hash_table.o obj/variables.o
HEADER_FILES = include/shell.h include/parser.h include/history.h include/hash_table.h include/variables.h
EXECUTABLE = sshell
LIBS = lib/libshell.so lib/libparser.so lib/libhistory.so lib/libhash_table.so lib/libvariables.so
LIBCFLAGS = $(CFLAGS) -D_REENTRANT -fPIC
CFLAGS = -Wall
CC = gcc
# End of configuration options
#What needs to be built to make all files and dependencies
all: $(EXECUTABLE)
#Create the main executable
$(EXECUTABLE): $(OBJS) $(LIBS)
$(CC) -o $(EXECUTABLE) obj/sshell.o -Llib -lparser -lshell -lhistory -lhash_table -lvariables
#Create the library files
$(LIBS): $(OBJS)
$(CC) $(LIBCFLAGS) -shared -o $(LIBS) $(OBJS)
#Recursively build object files
obj/%.o: src/%.c
$(CC) $(CFLAGS) -I./include/ -c $< -o $#
#Define dependencies for objects based on header files
#We are overly conservative here, parser.o should depend on parser.h only
$(OBJS) : $(HEADER_FILES)
clean:
-rm -f $(EXECUTABLE) obj/*.o lib/*.so lib/*.a
-rm -f .sshell_history.txt
run: $(EXECUTABLE)
(export LD_LIBRARY_PATH=lib; ./$(EXECUTABLE))
# End of Makefile
Thanks!
-Lily Banks
Edit:
Before I tried to change it, here is what I had with regards to library files.
$(LIBS): $(OBJS)
$(CC) -shared -o lib/libparser.a obj/parser.o
$(CC) -shared -o lib/libshell.a obj/shutil.o
$(CC) -shared -o lib/libhistory.a obj/history.o
$(CC) -shared -o lib/libhash_table.a obj/hash_table.o
$(CC) -shared -o lib/libvariables.a obj/variables.o
The problem with this was that it compiled each file five times which is not efficient at all. So what I was trying to do was do it all in one go.
Edit2:
#Create the library files
lib/libparser.so: obj/parser.o
$(CC) $(LIBFLAGS) -shared lib/libparser.a -o $#
lib/libshell.so: obj/shutil.o
$(CC) $(LIBFLAGS) -shared lib/libshell.a -o $#
lib/libhistory.so: obj/history.o
$(CC) $(LIBFLAGS) -shared lib/libhistory.a -o $#
lib/libhash_table.so: obj/hash_table.o
$(CC) $(LIBFLAGS) -shared lib/libhash_table.a -o $#
lib/variables.so: obj/variables.o
$(CC) $(LIBFLAGS) -shared lib/libvariables.a -o $#
Unfortunately, here is the error I am getting:
make: *** No rule to make target `lib/libvariables.so', needed by `sshell'. Stop.
Thoughts?
Edit3:
#Create the library files
lib/libparser.so: obj/parser.o
$(CC) $(LIBFLAGS) -shared $^ -o lib/libparser.a
lib/libshell.so: obj/shutil.o
$(CC) $(LIBFLAGS) -shared $^ -o lib/libshell.a
lib/libhistory.so: obj/history.o
$(CC) $(LIBFLAGS) -shared $^ -o lib/libhistory.a
lib/libhash_table.so: obj/hash_table.o
$(CC) $(LIBFLAGS) -shared $^ -o lib/libhash_table.a
lib/libvariables.so: obj/variables.o
$(CC) $(LIBFLAGS) -shared $^ -o lib/libvariables.a
This works but is there anything else I need to change? Thanks
You need one set of object files for each library. And the -o flag only takes one argument which is the output file, you are trying to output all the library files which you cannot do with one invocation of gcc.
You need to do something like:
lib/libshell.so: obj/sshell.o
$(CC) $(LIBFLAGS) -shared obj/sshell.o -o lib/libshell.so
lib/libparser.so: obj/parser.o
$(CC) $(LIBFLAGS) -shared obj/parser.o -o lib/libparser.so
for each of the libraries.
This line is completely wrong:
$(LIBS): $(OBJS)
$(CC) $(LIBCFLAGS) -shared -o $(LIBS) $(OBJS)
If you expanded all the variables, this line would look like this (adding line breaks for clarity):
lib/libshell.so lib/libparser.so lib/libhistory.so lib/libhash_table.so lib/libvariables.so: \
obj/shutil.o obj/parser.o obj/sshell.o obj/history.o obj/hash_table.o obj/variables.o
gcc -Wall -D_REENTRANT -fPIC -shared -o lib/libshell.so lib/libparser.so lib/libhistory.so \
lib/libhash_table.so lib/libvariables.so obj/shutil.o obj/parser.o obj/sshell.o obj/history.o \
obj/hash_table.o obj/variables.o
Which, it should be clear, is very not right. It's so not right I can't even really tell what you're trying to accomplish. Do you really want to create one shared library for every .o file, where each shared library contains a single .o? If so why are you trying to link both the .o files AND the shared libraries into a single executable?
If you explain what you are really trying to do, at a higher level, we can help.