Unknown IA32 assembly language Instructions - c

Question

I've been searching the internet for some time now and have come up with an odd problem.
Using a C compiler, I converted the following into assembly to later be converted to Y86:
#include <stdio.h>
int main(void)
{
int j,k,i;
for (i=0; i <5; i++) {
j = i*2;
k = j+1;
}
}
After the conversion, I get the following .s file:
.file "Lab5_1.c"
.section ".text"
.align 4
.global main
.type main, #function
.proc 04
main:
save %sp, -112, %sp
st %g0, [%fp-4]
ba,pt %xcc, .LL2
nop
.LL3:
ld [%fp-4], %g1
add %g1, %g1, %g1
st %g1, [%fp-8]
ld [%fp-8], %g1
add %g1, 1, %g1
st %g1, [%fp-12]
ld [%fp-4], %g1
add %g1, 1, %g1
st %g1, [%fp-4]
.LL2:
ld [%fp-4], %g1
cmp %g1, 4
ble %icc, .LL3
nop
mov %g1, %i0
return %i7+8
nop
.size main, .-main
.ident "GCC: (GNU) 4.8.0"
My question is about the instructions themselves. Many sites I've found have instructions similar to these, such as movl for mov, and cmpl for cmp. But some I can't make heads or tails of the other commands such as st, ba, pt, or ld to convert to Y86.
Any light on these instructions? Could it be a problem with the compiler?
For reference, I'm using Unix and command gcc -S "filename.c"

Answer 1

The st and ld instructions are obviously store-to and load-from memory. For the looks of things, ba is a branch instruction of some description.
In fact, based on the instructions being generated and a bit of quick research, it looks like you might be running on a SPARC architecture. The ld/st pair, ba and save are all instructions on that architecture.
The save instruction is actually the SPARC way of handling register save and restore when calling functions (the in/local/out method).
And that "slightly deranged" ba instruction is actually the branch-prediction version introduced in SPARC version 9, ba,pt %xcc, .LL2 meaning branch always (with a prediction that the branch will be taken) based on condition code (obviously some new definition of the word "always" of which I was previously unaware).
The opposite instruction ba,pn means predict that the branch will not be taken.
The presence of nop instructions following a branch is to do with the fact that SPARC does delayed branching - the instruction following a branch is actually executed before the branch is taken. This has to do with the way it pipelines instructions and would probably be considered a bug on any other (less weird) architecture :-)
All those factors taken together pretty well guarantee you're running on a SPARC, so I'd be looking up opcodes for that to figure out how best to transform it into Y86.
The other alternative is, of course, to generate x86 instruction. That may be possible by using a cross-compiler on your SPARC or simply compiling it on an x86 machine (assuming you have one available).