Makefile compile twice different define - c

Question

I'm trying to build two binaries with the same sources, just with a different define.
Basically what I'm doing right now is:
OBJ = $(SRC:.cpp=.o)
CPPFLAGS_S = $(INC) -Wall -Wextra -O3 -g -D SERVER
CPPFLAGS_C = $(INC) -Wall -Wextra -O3 -g -D CLIENT
server: CPPFLAGS= $(CPPFLAGS_S)
client: CPPFLAGS= $(CPPFLAGS_C)
server: $(OBJ)
g++ $(OBJ) -o $(NAME_S) $(CPPFLAGS_S) $(LIB)
client: $(OBJ)
g++ $(OBJ) -o $(NAME_C) $(CPPFLAGS_C) $(LIB)
all: server client
Obviously it's not working. What it's doing is compiling everything with the SERVER define, and because the .o files are already there, they will be used again to create the client binary, still using the SERVER define. I could use some help.

Answer 1

Well, it's a pretty fundamental tenet of filesystems that you can only have one file with a given name in the same directory. There's not much make can do about that!
So you have three choices: you can delete all the object files after you build each target, or you can create differently-named object files for each target, or you can build the objects into different subdirectories for each target.
Personally I prefer the latter, so you'd need to write new rules to explain to make how to create a file in a subdirectory:
SERVEROBJ = $(SRC:%.cpp=server/%.o)
CLIENTOBJ = $(SRC:%.cpp=client/%.o)
CXX = g++
CPPFLAGS = $(INC)
CXXFLAGS = -Wall -Wextra -O3 -g
server: CPPFLAGS += -DSERVER
client: CPPFLAGS += -DCLIENT
all: server client
server client:
$(CXX) $^ -o $# $(CXXFLAGS) $(LIB)
server: $(SERVEROBJ)
client: $(CLIENTOBJ)
server/%.o: %.cpp
mkdir -p $(#D)
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $# $<
client/%.o: %.cpp
mkdir -p $(#D)
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $# $<