Makefile for a single target with multiple .c and .h dependencies - c

Question

I have this hello-world.c that I'd like to compile to hello-world binary. But hello-world.c depends on a few functions defined in ../helpers/a.c and ../helpers/b.c, and each of those helpers include ../helpers/a.h and ../helpers/b.h respectively.
My current Makefile looks like
CC = #gcc
CFLAGS = -g -Wall -Wextra -Werror
CFLAGS +=
LDLIBS =
LDLIBS +=
OBJS = ../helpers/a.o ../helpers/b.o
SOURCES = hello-world.c
DESTS = hello-world
new: clean all
clean:
#rm -rf *.o */*.o $(DESTS)
all: $(OBJS) $(DESTS)
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $#
%: %.c
$(CC) $(CFLAGS) -o $# $<
but it doesn't work, returning make: *** No rule to make target `../helpers/a.o', needed by `all'. Stop.
I understand that Makefile doesn't seem to see the rule for %.o, but I don't see why.
Edit: Makefile debug:
alexandernst#stupidbox:/media/sf_procmon/procmon$ make --debug=b
GNU Make 3.81
Copyright (C) 2006 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
This program built for x86_64-pc-linux-gnu
Reading makefiles...
Updating goal targets....
File `new' does not exist.
File `clean' does not exist.
Must remake target `clean'.
Successfully remade target file `clean'.
File `all' does not exist.
File `../helpers/a.o' does not exist.
Must remake target `../helpers/a.o'.
make: *** No rule to make target `../helpers/a.o', needed by `all'. Stop.

Answer 1

This is much easier to get working if you put the Makefile in the parent directory. Then you can write something like this:
CC = gcc
CFLAGS = -g -Wall -Wextra -Werror
CPPFLAGS = -Ihelpers
DESTS = hello-world/hello-world
OBJS = helpers/a.o helpers/b.o hello-world/hello-world.o
# Do not make 'all' depend directly on object files.
all: $(DESTS)
# Clean rules should always be prefixed with '-' to avoid
# errors when files do not exist. Do not use 'rm -r' when
# there shouldn't be directories to delete; do not delete
# wildcards when you can use explicit lists instead.
# Never use '#'.
clean:
-rm -f $(OBJS) $(DESTS)
# An explicit linkage rule is needed for each entry in DESTS.
hello-world/hello-world: hello-world/hello-world.o \
helpers/a.o helpers/b.o
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LIBS)
# The main function of these dependency lists is to prevent
# Make from deleting object files after each build. We also
# take the opportunity to specify header dependencies.
# We rely on the built-in %.o:%.c rule for commands.
hello-world/hello-world.o: hello-world/hello-world.c \
helpers/a.h helpers/b.h
helpers/a.o: helpers/a.c helpers/a.h
helpers/b.o: helpers/b.c helpers/b.h
# This tells Make that 'all' and 'clean' are not files to be created.
.PHONY: all clean
For further exposition of this technique, see the watershed paper 'Recursive Make Considered Harmful' and the associated implementation notes.

Answer 2

I managed to fix my Makefile:
CC = gcc
CFLAGS = -g -Wall -Wextra -Werror
CFLAGS +=
LDLIBS =
LDLIBS +=
OBJS = ../helpers/a.o ../helpers/b.o hello-world.o
SOURCES = hello-world.c
DESTS = hello-world
new: clean all
clean:
#rm -rf *.o */*.o ../helpers/*.o $(DESTS)
all: $(DESTS)
hello-world: $(OBJS)
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LIBS)
One of the problems was that a bad clean rule that I wrote had wiped a.c and b.c and Makefile was acting because of this.