I wanna use some functions which are defined in libvmi/driver/xen.c file, in process-list.c file,but I don't know where in Makefile I should link this two ".c" files.
I know how to do this in a simple Makefile but I couldn't find something like that in this Makefile to add linking part of libvmi/driver/xen.c and process-list.c.
This Makefile belongs to a project with several Makefiles.
Thanks for any help!
## Source directory
SUBDIRS =
INCLUDES = -I$(top_srcdir)
AM_LDFLAGS = -L$(top_srcdir)/libvmi/.libs/
LDADD = -lvmi -lm $(LIBS)
c_sources = process-list.c \
libvmi/driver/xen.c
bin_PROGRAMS = module-list process-list map-symbol map-addr dump-memory
module_list_SOURCES = module-list.c
process_list_SOURCES = $(c_sources)
map_symbol_SOURCES = map-symbol.c
map_addr_SOURCES = map-addr.c
dump_memory_SOURCES = dump-memory.c
You shouldn't need to link two .c files, you need to compile them and then link the .o files. If your project makefile is generated, perhaps this happens automatically, if not you would mainly need to add the new .c files to the build.
Related
I have about 39 Fortran F90 source files and 35 Fortran 77 Lapack related files. I am using include statement in my main program to connect all these files.
I have created a batch file make.bat with command ifort "MDL HydroD.F90" which compiles my code and generates the mdlhydrod.exe file. In the process the Fortran compiler creates many .mod and .obj build files which makes it difficult to manage. I would like to put my source files under a directory Source and lapack library files in a directory lapack and build files in a directory Debug.
Could anyone help me modify my make.bat file so that ifort looks at Source directory and build in Debug directory.
Thank you for help.
Currently using make.bat has only one line of command:
File Name: make.bat
ifort "MDL HydroD.F90"
Working on a make file to be used with nmake (incomplete):
File Name: make.mak:
#Make File for MDL HydroD
# Compiler options
FC := ifort
VPATH := src
BINDIR := bin
$(BINDIR):
mkdir -p $(BINDIR)
clean:
#rm -rf $(BINDIR)
Because you are using a strange way of working with source files, which you showed in your other question, it will be very difficult to change this.
For recapitulation, you include everything in a single source file using the include statement. This looks pretty unfortunate to me and I commented on that there. If you have one source file, you are forced to build it with one command, there is no place for any fine control. This is not the issue of a bash or bat script vs. Makefile.
You can probably still keep some files included in some groups that are logically similar, if you need no finer control on that, but I see not much reason for that.
Remove the includes or at least the relevant ones. Then you can just do
ifort Source/the_source_file1 -c Output/name_of_obj1 -module the_directory_for_modules -I the_directory_for_modules -other_flags
for every file. And then in the end:
ifort Output/name_of_obj1 Output/name_of_obj2 Output/name_of_obj3 .... -o the_result
In Scons (which I would use) it would be like this (tested on couple of dummy files). The file Sconstruct:
import os
env = Environment(tools=['default','ifort'])
env.Append(ENV = {'PATH' : os.environ['PATH']})
try:
env.Append(ENV = {'LIBRARY_PATH' : os.environ['LIBRARY_PATH']})
except:
pass
env.Append(F90FLAGS='-g -fast') #whatever flags you need
env.Append(FORTRANFLAGS='-g -fast') #whatever flags you need
outdir = "Output/"
srcdir = "Sources/"
lapackdir = "lapack/"
objs = []
for file in os.listdir(srcdir):
objs += env.Object(target=outdir+os.path.splitext(file)[0], source=srcdir+file)
for file in os.listdir(lapackdir):
objs += env.Object(target=outdir+os.path.splitext(file)[0], source=lapackdir+file)
env.Append(FORTRANMODDIR = outdir)
objs = filter(lambda o: str(o)[-4:] != '.mod', objs)
prg = env.Program(target="bin/result.exe", source= objs)
Default(prg)
I have a folder called UnitTest. I have several .c files in it. All files contain function 'main'.
Using makefile, I want to compile all .c files of that folder together.
But these files have dependency on other C files which are in different folder.
How can I write make file for this?
eg.
Common\*.c - generate object file
App\*.c - generate object file. - refers to .o files of Common directory
UnitTest\.c - these files should be compiled as executables. Refer *.o from directory App and Common.
Update:
Header files are in seperate directory called \Include
I need a single makefile for this. Please help.
As per the standards every directory will contain one Makefile. So you can have three Makefiles for this job done if you have three directories.
(d) common
|
|---(f) common.h
|---(f) common.c
|---(f) Makefile --- MAkefile for the common folder.
(d) app
|
|---(f) app.h
|---(f) app.c
|---(f) Makefile
(d) unittest
|
|---(f) unittest.h
|---(f) unittest.c
|---(f) Makefile
(f) Makefile --- invoke all makefiles in the mentioned order.
If you want one Makefile to happen all these done, you can do in that way also. Here you have to compile the files by providing paths of the files. order is most impotent.
This is complicated, so we will take it in stages. First, building the object files:
CFLAGS += -I/include
vpath %.h /include
This should be enough to build any object file in Common/, Apps/ or UnitTest/. Test this before going further.
Now to build all of the objects in Common/:
COMMONSOURCES := $(wildcard Common/*.c)
COMMONOBJECTS := $(COMMONSOURCES:.c=.o)
all: $(COMMONOBJECTS)
Test this before going further.
Remove that all rule, and put in a rule for the Common library. (We'll use a static library for now, since it's a little simpler.)
Common/libCommon.a: $(COMMONOBJECTS)
ar -cvq $# $^
Test that much, tell us in the comments how it worked, then we'll build Apps library and the UnitTest executables.
I have source code in one directory and have a makefile in a different directory. I am able to compile the code using the make system's vpath mechanism. The .o files are being created in the same folder where the makefile is. But I want to move those .o files to a different directory called obj. I tried the following:
vpath %.o obj
However, they are still being created in the same folder as the makefile. Can anyone help me to solve this issue?
Here are some highlighted lines of the makefile:
PATH_TO_OBJ:- ../obj
SRC :- .c files
OBJS :- $(SRC:.c = .o)
.c.o = $(CC) $(CFLAGS) -c
exe: cc $(LFLAGS) -o $(PATH_TO_OBJ) $(SRC).
After this also, .o file is creating in same folder of Makefile. Not moving to obj
-o option defines where to save the output file, produced by a gcc compiler.
gcc main.c -c -o path/to/object/files/main.o
Make's VPATH is only for finding source files. The placement of object files is up to the thing that is building them. There's a nice description at http://mad-scientist.net/make/vpath.html (I see someone beat me to posting this in a comment).
The *BSD build systems use variants of make that can place object files (and other generated files, including C sources from lex and yacc variants) in /usr/obj automatically. If you have access to that version of make, that will likely be a good way to deal with whatever underlying problem you are trying to solve.
I am having a 1.c 2.c....n.c files and having its dependencies .h file also... i know to create make file for multiple c files.But i don't how to create make file for which the c files are linking to .h files. If i try the makefile which i know it will give error like
make: *** No rule to make target '2.h', needed by '2.o' .Stop.
and I don't need this type of makefile also.
program: main.o dbAdapter.o
gcc -o program main.o dbAdapter.o
main.o: main.c dbAdapter.h
gcc -c main.c
dbAdapter.o dbAdapter.c dbAdapter.h
gcc -c dbAdapter.c
This will be good for 4 or 5 files. But if I have a large number of files, what is the best solution?
You can link all your .h in the Makefile by this way :
Put all the .h in a same file (that we called "Include" for the exemple)
Add this in your Makefile : gcc *.c -I/path/Include -iInclude
Ps: Your way to compile your .c file is a bit strange.
Usually we use this:
SRC = 1.c
2.c
n.c
OBJ = $(SRC:.c=.o)
all: $(OBJ)
gcc $(SRC) -I/path/Include -iInclude (where path is the location of your file called "Include")
As long as I'm working with C, I never wrote make files that includes header files (.h) the header files are here to expose some of the data structure and methods, constants that are needed in other C modules.
You don't need to create rules for header files, all you have to do is build the .o objects then the liker will do the magic for you when you create the executable file.
If you need some help crating a make file you can explain here what you wanna build and I'll send you a hint.
Cheers.
If your header files are not in current directory and you included it in Makefile, Make starts looking for header files in default location but it is not able to find them in your case.
you should put 2.h header files in current directory to avoid this search.
I am working on a C project which contains around 200 .c files and some .h files. Not all of these 200 files are required in the final product. Currently around 180 files needs to be compiled. We have a file "compile_only_these.c" which includes these 180 *.c files required for the project. Our makefile compiles only this file instead of individual .c files.
/* file: compile_only_these.c*/
#include "file1.c"
#include "file2.c"
.
.
.
#include "file180.c"
But I think including .c files is a bad idea. Because every time I modify any of these files, all files are compiled again.
Can you suggest a better way to compile these files.
More info:
All .c files are in same folder "../project/src"
I keep adding new .c files which are required to be compiled. I dont want to modify Makefile every-time I add a new file.
I still want to keep those 20 .c files which I am not compiling right now. I may use it in future. Deleting these files are moving them to other directory is not a solution
What you need is a variable in the makefile, a list of required object files, like this:
OBJS := file1.o file2.o ... file180.o
You can have Make construct it from the compile_only_these.c file like this:
OBJS := $(shell sed -e '/\#include/!d' -e 's/\#include "\(.*\)\.c"/\1.o/' compile_only_these.c)
Do you also need a hand with the rule that uses these objects to construct the final product?
As already mentioned, it's sort of a weird way to manage a project, but given what you have to work with, you might try something along this approach...
CC = gcc
OBJFILE = myprog
# Tweak to match whatever you compile with normally
CFLAGS = -O2 -Wall -std=c89 -pedantic
LDFLAGS= # Extra flags here, for example -lm -pthread
RM = rm -f
SRCS = $(wildcard *.c)
OBJS = $(SRCS:.c=.o)
$(OBJFILE):$(OBJS)
$(CC) -o $# $^ $(LDFLAGS)
clean:
$(RM) core *~ $(OBJS) $(OBJFILE)
You will obviously need to adjust the path(s) for the specifics of your build hierarchy if you want to do more in your make than just compile this list of files, but this is a general approach for grabbing all files with wildcard substitution.