GNU Make: different dependencies of several binaries in the same target? - c

Question

First of all, I'm not familiar with GNU Make, so if I state some concept ridiculously wrong, please correct them instead of teasing me, thanks.
I want to have a default target that builds several executables with different dependencies, but I can't figure it out. Here is a minimal example I am using:
CC = gcc-4.8
CFLAGS = # some compiler flags
LDFLAGS = # some linker flags
SOURCES = prog1.c prog2.c
OBJECTS = $(SOURCES:.c=.o)
TARGET = prog1 prog2
$(TARGET) : $(OBJECTS)
$(CC) $(CFLAGS) -o prog1 prog1.o $(LDFLAGS)
$(CC) $(CFLAGS) -o prog2 prog2.o $(LDFLAGS)
.PHONY: clean
clean:
#rm -f $(TARGET) $(OBJECTS) core
But, as you can see, though prog2 is not at all related to prog1.c, editing prog1.c will result in the relinking of prog2. Is there any way to prevent this?
(Also, I would really appreciate it if someone can direct me to a good tutorial to GNU Make. The official documentation is huge...)

Answer 1

Each target has to have its own set of prerequisites; if you write:
foo bar: biz baz
that means "foo depends on biz and baz, and bar also depends on biz and baz". You want to write:
prog1: prog1.o
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LDLIBS)
prog2: prog2.o
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LDLIBS)
Alternatively, you can write both targets in the same rule and define the prerequisites separately:
prog1 prog2:
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LDLIBS)
prog1: prog1.o
prog2: prog2.o
There are lots and lots of ways to make this more sophisticated and reduce typing. That's kind of what make is all about.
Update:
To build two targets at the same time by default, use
all: prog1 prog2
prog1 prog2:
$(CC) $(CFLAGS) $(LDFLAGS) -o $# $^ $(LDLIBS)
prog1: prog1.o
prog2: prog2.o
where all is the first target.