I am working on winexe project currently. winexe compiles windows C code on linux using -mno-cygwin as CFLAGS .
following is Makefile under directory winexesvc :-
CFLAGS=-mno-cygwin -Os
LDFLAGS=-mno-cygwin -s -Os
CC_WIN32 := $(shell bash -c 'which {i386,i586}-{mingw32,mingw32msvc}-gcc')
CC_WIN64 := $(shell bash -c 'which {x86_64,amd64}-{mingw32,mingw32msvc}-gcc')
all: winexesvc32_exe.c winexesvc64_exe.c
winexesvc32.exe: winexesvc32.o service32.o
$(CC_WIN32) $(LDFLAGS) -o $# $^
winexesvc64.exe: winexesvc64.o service64.o
$(CC_WIN64) $(LDFLAGS) -o $# $^
%32.o: %.c
$(CC_WIN32) -c $(CPPFLAGS) $(CFLAGS) -o $# $^
%64.o: %.c
$(CC_WIN64) -c $(CPPFLAGS) $(CFLAGS) -o $# $^
winexesvc32_exe.c: winexesvc32.exe bin2c.exe
./bin2c.exe winexesvc32_exe winexesvc32.exe > $#
winexesvc64_exe.c: winexesvc64.exe bin2c.exe
./bin2c.exe winexesvc64_exe winexesvc64.exe > $#
bin2c.exe: bin2c.c
gcc -s -o $# $^
clean:
-#rm *.exe *.o *_exe.c
The entire code compiles and run successfully when no modification is done.
But,whenever I replace winexsvc.c file or winexesvc64_exe.c file or winexesvc32_exe.c
(I need to modify these 3 files). It shows following error when I replace winexesvc.c with modified code. The modified code dosen't call any other file or any function outside the file.
So, the problem is when I do some modifications in above mentioned 3 files, I get above mentioned errors.
Any Idea why this is happening ?
P.S :- I have read other post regarding error of -mno-cygwin option in gcc.
but those are not relevant to my problem.
additional information :-
[I have got this from Makefile of winexesvc folder under winexe.]
Solved :-
I used i586-mingw32msvc-gcc command along with suitable flags to compile every file by hand then linking it accordingly.
Got , the required results.
Related
I have a basic Makefile setup for C OpenGL programming but when running there are 2 files passed to clang that shouldnt exist and i have no idea why. The problem happened after i added glad and glfw to the project.
code:
CC = clang
`CCFLAGS = -lGL -lglfw -std=c++20 -v -Wall -Wextra -Wepedantic -g -lgdi32
LDFLAGS = lib/glad/src/glad.o lib/glfw/src/libglfw3.a -lgdi32 -lm
SRC = $(wildcard src/*.c)
OBJ = $(SRC:.c=.o)
BIN = bin
all: libs build
libs:
cd lib/glad && $(CC) -o src/glad.o -Iinclude -c src/glad.c
cd lib/glfw && cmake . -G 'Unix Makefiles' && make
build: $(OBJ)
$(CC) -o $(BIN)/build $^ $(LDFLAGS)
%.o %.c:
$(CC) -o $# -c $< $(CCFLAGS)
run:
./bin/build.exe
ERROR:
clang: error: no such file or directory: 'all.o'
clang: error: no such file or directory: 'libs'
clang: error: no such file or directory: 'build'
When asking questions please include the command you typed, the command make printed, plus at least the first and last few lines of error messages (properly formatted as code blocks).
I'm assuming that the extra quote character is an error in your cut and paste; please take a moment to review your question after you post it (or even better, using the preview before you post it). You are writing this one time, but tens or hundreds of people will spend their time reading it. Please be considerate enough to make it easy for them.
Your problem is this:
%.o %.c:
$(CC) -o $# -c $< $(CCFLAGS)
You want to say "build a .o file from a .c file using this rule", but %.o %.c: says instead, "build both a .o and a .c file, from nothing, using this rule".
You need:
%.o: %.c
$(CC) -o $# -c $< $(CCFLAGS)
I would like my makefile to compile two sources, osmprun.c and echoall.c.
Currently it's just compiling osmprun.c, which creates errors.
Im at my wits end, Im not experienced with makefiles at all and I just don't understand what im doing wrong.
My makefile is:
CC=gcc
CFLAGS= -Wall -Wconversion -g
LIBS=-lm -lpthread
DEPS=
BUILD_DIR := build
SRCS := osmprun.c echoall.c
OBJS := $(addprefix $(BUILD_DIR)/,$(patsubst %.c,%.o,$(SRCS)))
$(BUILD_DIR)/%.o: %.c $(DEPS)
mkdir -p $(BUILD_DIR)
$(CC) -c $(CFLAGS) $< -o $#
echoall: $(OBJS)
mkdir -p $(BUILD_DIR)
$(CC) $(CFLAGS) $< $(LIBS) -o $#
osmprun: $(OBJS)
mkdir -p $(BUILD_DIR)
$(CC) $(CFLAGS) $< $(LIBS) -o $#
.PHONY: clean
clean:
rm -f $(BUILD_DIR)/*.o *~ core
test:
./osmprun
Can somebody help me figure out my mistake and explain what the problem is?
EDIT:
I've now changed the part where it is supposed to compile the two files to:
echoall: echoall.c
$(CC) $(CFLAGS) $^ $(LIBS) -o $#
osmprun: osmprun.c
$(CC) $(CFLAGS) $^ $(LIBS) -o $#
But it is still only compiling echoall, not osmprun
It would help greatly if you included the command you typed and the output you got, and what you wanted to get, especially because your terminology is not quite accurate. It's not true that make is not compiling all the object files. The problem is at the link stage.
However, I don't understand what your makefile is intended to do. You have two targets and they both depend on the SAME set of object files:
echoall: $(OBJS)
osmprun: $(OBJS)
Do you need to link both of those object files together? If so then what is the difference between the echoall program and the osmprun program, if they both contain the same set of object files?
Or, do you want to create the echoall program from the echoall.c source file and the osmprun program from the osmprun.c source file? If so, why do you list both objects as a prerequisite for both programs?
In any event your problem is here:
echoall: $(OBJS)
mkdir -p $(BUILD_DIR)
$(CC) $(CFLAGS) $< $(LIBS) -o $#
osmprun: $(OBJS)
mkdir -p $(BUILD_DIR)
$(CC) $(CFLAGS) $< $(LIBS) -o $#
(the mkdir here are useless: you know that the directory already exists because you already built the object files, but they don't hurt anything).
The problem is you're using $< which is the first prerequisite. Because both prerequisite lists are the same, you're building both programs from the same, single source file.
If you want both programs to contain both object files, you should use $^ here not $<. If you want each program to contain only its related object file, you should change the prerequisites to contain only the object file it should be built from (and also use $^).
I'm trying to make a Makefile for my program. It is so difficult because i've read a lot of guide but none is clear. I have 3 files : main.c , library.c , library.h . Main.c and library.c depend on library.h . The structure of my directory project is formed by :
MyProject directory -> Build directory and Exercise1 directory -> all of my files . In compiler I wrote make and it compiled ; then when I write make execute command, it gives me this error:
cd ../build; ./test
Error: No such file or directory
makefile:23: recipe for target 'execute' failed
make: *** [execute] Error 1
MAKEFILE
CC=gcc
CFLAGS=-Wall
ODIR=../build
DIR = build
.PHONY: all
all: main.o library.o test
$(ODIR)/%.o: %.c $(DEPS)
$(CC) -std=c99 -c -o $# $< $(CFLAGS)
library.o: library.c library.h
$(CC) -std=c99 -c -o $(ODIR)/$# $< $(CFLAGS)
main.o: main.c library.h
$(CC) -std=c99 -c -o $(ODIR)/$# $< $(CFLAGS)
test: $(ODIR)/library.o $(ODIR)/main.o
$(CC) -std=c99 -o $(ODIR)/$# $^ $(CFLAGS)
execute:
cd $(ODIR); ./test
clean:
rm -f $(ODIR)/*.o
These lines:
execute:
cd $(ODIR); ./test
tell make that, when you give the command make execute, it should change the working directory to $(ODIR) and then execute ./test, which means to execute the file test in the current working directory. However, there is no file test in the $(ODIR) directory because you have not built it yet.
You can make that file by executing make test, but that is a bad way to do it. It is better to tell make that the execute target depends on $(ODIR)/test:
execute: $(ODIR)/test
cd $(ODIR); ./test
Then we should change the rule for test to $(ODIR)/test:
$(ODIR)/test: $(ODIR)/library.o $(ODIR)/main.o
$(CC) -std=c99 -o $(ODIR)/$# $^ $(CFLAGS)
Next, delete the rule for all and the .PHONY rule. A rule for all should be used when a makefile can make several different final targets, like ProgramA, ProgramB, and ProgramC, and you want one target that makes all of them. It should not be used to make all of the intermediate object files for a target. The intermediate files should arise out of the rules for building a final target.
Then delete the rules for library.o and main.o. Those are names for files in the current directory, but you are building in $(ODIR). We will let the pattern rule for $(ODIR)/%.o build those.
But we need to fix the pattern rule. It uses DEPS, but that is not defined. Add a line above that says what all the object files depend on:
DEPS=library.h
Nothing in the makefile uses DIR, so delete the line DIR = build.
Finally, you might want to put the execute target first, so that it is the default. Then your makefile is:
CC=gcc
CFLAGS=-Wall
ODIR=../build
DEPS=library.h
execute: $(ODIR)/test
cd $(ODIR); ./test
$(ODIR)/%.o: %.c $(DEPS)
$(CC) -std=c99 -c -o $# $< $(CFLAGS)
$(ODIR)/test: $(ODIR)/library.o $(ODIR)/main.o
$(CC) -std=c99 -o $(ODIR)/$# $^ $(CFLAGS)
clean:
rm -f $(ODIR)/*.o
You might also change the command for clean to remove test:
rm -f $(ODIR)/*.o $(ODIR)/test
After going through the LWIP documents, I wrote a simple tcp echo server code. To compile it and create an executable I wrote the following Makefile. Now, when I run the command make all, it gives error for each of .c files included in the makefile.
The file structure is as follows:
1. tcp_server.c is the main file where I create the tcp server.
2. It uses the tcp_new(), tcp_bind() etc functions defined in "lwip-1.4.1/src/core/lwip/tcp.c" and "lwip-1.4.1/src/core/lwip/tcp_out.c" and I have given the paths for compilation accordingly.
I am just a beginner in writing makefiles and have written the following file going through the GNU Make documentation.
CC=gcc
CFLAGS= -g -Wall
LWIPDIR=../lwip-1.4.1/src
TARGET=tcp_server
INCLUDES= -I../lwip-1.4.1/src/include -I../STABLE-1_4_0/ports/unix/proj/lib\
-I../STABLE-1_4_0/ports/unix/include -I../lwip-1.4.1/src/include/ipv4
LFLAGS= -L../STABLE-1_4_0/ports/unix/proj/lib/liblwip.so
#LIBS= -llwip
COREFILES=$(LWIPDIR)/core/tcp.c $(LWIPDIR)/core/tcp_out.c
VPATH = $(LWIPDIR)/core
OBJS = tcp_server.o tcp.o tcp_out.o
MAIN=tcp_server
all : edit
edit : $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o edit $(OBJS) $(LFLAGS)
tcp_server.o : tcp_server.c tcp.o tcp_out.o
$(CC) $(CFLAGS) $(INCLUDES) -c tcp_server.c $(LFLAGS)
tcp.o : $(LWIPDIR)/core/tcp.c
$(CC) $(CFLAGS) $(INCLUDES) -c $(LWIPDIR)/core/tcp.c $(LFLAGS)
tcp_out.o : $(LWIPDIR)/core/tcp_out.c
$(CC) $(CFLAGS) $(INCLUDES) -c $(LWIPDIR)/core/tcp_out.c $(LFLAGS)
clean :
rm -f *.o
All the files include certain headers defined in "lwip-1.4.1/src/include" and I given the arguments to -I accordingly. However on running make, the output shows "Undefined reference to" all the functions which are defined in the lwip header files. What could be the reason? Where I am going wrong?
Thank you for all the help.
UNDEFINED REFERENCE is a linker error so you should;
For gcc you should use -L to specify the directory your libraries are contained and use -l to link a particular library. For example change the line in your makefile;
LFLAGS= -L../STABLE-1_4_0/ports/unix/proj/lib
remove the comment before LIBS and change this target
edit : $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o edit $(OBJS) $(LFLAGS) $(LIBS)
I have three files: program.c, program.h and headers.h.
program.c includes program.h and headers.h.
I need to compile this on Linux using gcc compiler. I'm not sure how to do this. Netbeans created one for me, but it's empty.
Interesting, I didn't know make would default to using the C compiler given rules regarding source files.
Anyway, a simple solution that demonstrates simple Makefile concepts would be:
HEADERS = program.h headers.h
default: program
program.o: program.c $(HEADERS)
gcc -c program.c -o program.o
program: program.o
gcc program.o -o program
clean:
-rm -f program.o
-rm -f program
(bear in mind that make requires tab instead of space indentation, so be sure to fix that when copying)
However, to support more C files, you'd have to make new rules for each of them. Thus, to improve:
HEADERS = program.h headers.h
OBJECTS = program.o
default: program
%.o: %.c $(HEADERS)
gcc -c $< -o $#
program: $(OBJECTS)
gcc $(OBJECTS) -o $#
clean:
-rm -f $(OBJECTS)
-rm -f program
I tried to make this as simple as possible by omitting variables like $(CC) and $(CFLAGS) that are usually seen in makefiles. If you're interested in figuring that out, I hope I've given you a good start on that.
Here's the Makefile I like to use for C source. Feel free to use it:
TARGET = prog
LIBS = -lm
CC = gcc
CFLAGS = -g -Wall
.PHONY: default all clean
default: $(TARGET)
all: default
OBJECTS = $(patsubst %.c, %.o, $(wildcard *.c))
HEADERS = $(wildcard *.h)
%.o: %.c $(HEADERS)
$(CC) $(CFLAGS) -c $< -o $#
.PRECIOUS: $(TARGET) $(OBJECTS)
$(TARGET): $(OBJECTS)
$(CC) $(OBJECTS) -Wall $(LIBS) -o $#
clean:
-rm -f *.o
-rm -f $(TARGET)
It uses the wildcard and patsubst features of the make utility to automatically include .c and .h files in the current directory, meaning when you add new code files to your directory, you won't have to update the Makefile. However, if you want to change the name of the generated executable, libraries, or compiler flags, you can just modify the variables.
In either case, don't use autoconf, please. I'm begging you! :)
For example this simple Makefile should be sufficient:
CC=gcc
CFLAGS=-Wall
all: program
program: program.o
program.o: program.c program.h headers.h
clean:
rm -f program program.o
run: program
./program
Note there must be <tab> on the next line after clean and run, not spaces.
UPDATE Comments below applied
all: program
program.o: program.h headers.h
is enough. the rest is implicit
The simplest make file can be
all : test
test : test.o
gcc -o test test.o
test.o : test.c
gcc -c test.c
clean :
rm test *.o
Depending on the number of headers and your development habits, you may want to investigate gccmakedep. This program examines your current directory and adds to the end of the makefile the header dependencies for each .c/cpp file. This is overkill when you have 2 headers and one program file. However, if you have 5+ little test programs and you are editing one of 10 headers, you can then trust make to rebuild exactly those programs which were changed by your modifications.