I am trying to make an object file via "cc -c -o " but I get the following statement ,what should I do to solve this,thanks in advance
~/hedor1>lex -t example.l > example.c
~/hedor1>cc -c -o example.o example.l
cc: example.l: linker input file unused because linking not done
the first line to produce the example.c is working and I get the .c file but when I write the second line I get the above!
You are passing the flex source to the compiler, which apparently interprets it as being a linker input file, and complains because you told the compiler not to do the linking step.
The second command should have been:
cc -c -o example.o example.c
Related
I've used makefile to generate file.
gcc -c hello.c -o hello
and fixed the permission problem through:
chmod a+x ./hello
However, when I want to execute "hello" file.
./hello
the system told me that "cannot execute binary file"
Can someone help me? I am looking forward your reply badly.
The -c argument to gcc produces an object file which you later on must link in order to produce an executable. You can not execute the object file you produced.
Instead, to compile and link at the same time, suitable when you only have 1 .c file, do
gcc hello.c -o hello
Or if you want to break it down to separate compilation and linking steps, do
gcc -c hello.c -o hello.o
gcc hello.o -o hello
Check whether the GCC compiler is installed in your system correctly or not.
gcc -v
Compile your file:
gcc filename.cpp -o any-name
Running your program:
./any-name
As an alternative to compiling and linking at the same time you can use make:
make hello
Note: without the .c extension.
The terminal output should be:
cc hello.c -o hello
Suppose there are 2 c program named abc.c and xyz.c . Now we want to work with the 2 executables at a time. So we change the name of the ./a.out using
gcc -g abc.c -o abc
gcc -g xyz.c -o xyz
Even gcc -o abc abc.c works.
What does the -g and -o in the above commands specify or describe?
What is the significance of -g and -o in the command for renaming ./a.out file.
Thanks in advance.
-g means to leave debugging information in the output file, it's unrelated to renaming.
-o means to put the result in the specified file instead of the default filename (abc.o for object files, a.out for linked executable files).
From https://gcc.gnu.org/onlinedocs/gcc/Option-Summary.html:
-g
Produce debugging information in the operating system's native format (stabs, COFF, XCOFF, or DWARF). GDB can work with this debugging information.
-o file
Place output in file file. This applies to whatever sort of output is being produced, whether it be an executable file, an object file, an assembler file or preprocessed C code.
-g starts becoming useful once you use debuggers such as gdb and lldb. When you attach to a running program and advancing one line at a time printing/altering the state as it changes.
if we specify -g option while compiling, debugging symbols will be available in the output file which will be useful when you try to debug using GDB.
If we won't specify -o option, the output will be placed in default a.out file. So if we run
gcc a.c - output will be in a.out
gcc b.c - output is a.out which is replacing old a.out file
If you want the output not to be a.out file, you can give -o option while compiling
gcc abc.c -o a
-o and -g options are not related.
I wrote a C programm and saved it with a .c extension.
Then I compiled with the gcc but after that I only see my .c file and an .exe file. The program runs perfectly. But where is the .o file that I learned in theory? Has it been overwritten to .exe and all done by the gcc in on step? (Preprocessing, compiling, assembling and linking)
I'm on a VM running Debian.
By default, gcc compiles and links in one step. To get a .o file, you need to compile without linking. That's done with the -c option.
Suppose you want to compile two files separately, then link them. You would do the following:
gcc -c file1.c # creates file1.o
gcc -c file2.c # creates file2.o
gcc -o myexe file1.o file2.o
If you want just the output of the preprocessor, use the -E option along with the -o to specify the output file:
gcc -E file1.c -o file1-pp.c # creates file1-pp.c
Compile and link in two steps:
gcc -Wall -c tst.c
gcc tst.c -o tst
After first command you'll get a .o file.
if you did something like gcc test.c then it produces only the executable file (in order to compile only, see the -c option)
here is steps on compiling with gcc to create a .o file from your C file:
http://www.gnu.org/software/libtool/manual/html_node/Creating-object-files.html
I was reading about ELF files on the net and am stuck in understanding a standard command to generate an ELF file.
Till now I have been running my code using > gcc test.c -o test.o .Thats it!!
One article says:
gcc -c test.c // will generate ELF file test.o
Now -o option is to tell the compiler to create an executable ( which is not ELF)
Another article says:
gcc -c test.c -o test.o // will generate ELF test.o -> here's where I am confused.
-o should always generate Executable.
The option -c tells GCC to generate an object file. This object file is only the compiled code from the source file test.c, not a complete program. To generate a complete program you need to link the object file. Or not use the -c option.
The -o option tells GCC what to name the output file, no matter what kind of output file it is.
So, to generate an executable file from a single source file, the simplest command is
$ gcc test.c
The above command will create an executable named a.out in the current directory. To name the output file something else you use the -o option:
$ gcc test.c -o myprogram
The above commands names the executable program myprogram.
To use the intermediate step with object files you use the -c option, and then use a separate step to link the program, like
$ gcc -c test.c
$ gcc test.o -o myprogram
The above two commands is the same as the single command gcc test.c -o myprogram.
I'm new to makefiles, so I apologize in advance if this is a silly question. Also I removed most variables from my makefile because they weren't working properly (gnu make tells me that $(myvar) should be completely replaces by the value of myvar, however the output of make was showing me that this was not happening), so I apologize for the ugliness and the more than 80 character lines.
acolibobj = acoLibInit acoGlobalDefs
acolibinterface: $(acolibobj).o
acoLibInit.o:
gcc -fPIC -g -c -Wall -I/usr/include/dc1394 -o acoLibinit.o acoCommands/acoLibInterface/acoLibInit.c
acoGlobalDefs.o:
gcc -fPIC -g -c -Wall -I/usr/include/dc1394 -o acoGlobalDefs.o acoCommands/acoLibInterface/acoGlobalDefs.c
When I run this makefile I get:
gcc -fPIC -g -c -Wall -I/usr/include/dc1394 -o acoLibinit.o acoCommands/acoLibInterface/acoLibInit.c
cc acoLibInit.o -o acoLibInit
gcc: acoLibInit.o: No such file or directory
gcc: no input files
make: *** [acoLibInit] Error 1
So far as I can tell, what's happening is that make is trying to compile AND link, even though I explicitly added the -c flag. When I run "gcc -fPIC -g -c..." myself (from bash), I do not get any problems at all. Why does make go on to try "cc acoLibInit.o -o acolibInit"?
make is trying to build acoLibInit. It probably has built-in rule that specifies "whatever" can be produced by linking "whatever.o", which is why you get that cc line.
This line:
acolibinterface: $(acolibobj).o
expands to:
acolibinterface: acoLibInit acoGlobalDefs.o
(note the absence of .o on the first dependency). This is why it's trying to link acoLibInit.
Try this:
acolibinterface: $(addsuffix .o,$(acolibobj))
if you want only the .o files as dependencies for that target.
$(acolibobj).o expands to acoLibInit acoGlobalDefs.o. Thus, you're really saying:
acolibinterface: acoLibInit acoGlobalDefs.o
Simply define acolibobj = acoLibInit.o acoGlobalDefs.o and use acolibinterface: $(acolibobj).