Compiling a list of files with many directories - c

Question

i've been banging my head over this issue today.
I have many c files in many directories. They all need to be compiled and linked to a library.
Here is a hypothetical layout of the files:
main_dir/
thing1/
thing1.c
thing2/
thing2.c
thing3/
thing3.c
MakeFile
I have a makefile that "finds" these files and generates the necessary objects, however, the same c file is always used as the input.
This is what the Makefile looks like (the contents of each file are a function each that uses puts()):
C=gcc
CFLAGS=-Wall -g
OBJDIR=obj
SRC=$(shell find src/ -type f -name "*.c")
SRC_DIRS=$(shell find src/ -type f -name "*.c" -exec dirname {} \; | uniq)
OBJS=$(SRC:%.c=${OBJDIR}/%.o)
$(OBJS) : $(SRC)
#echo Compiling : $<
$(C) -c $(CFLAGS) -o $# $<
clean:
rm -fv $(OBJS) thingy.a
folders:
$(call build_dirs)
all: folders $(OBJS)
ar -r -o thingy.a $(OBJS)
define build_dirs
for dir in $(SRC_DIRS); do \
mkdir -pv $(OBJDIR)/$$dir; \
done
endef
The output from making:
for dir in src/thing1 src/thing2 src/thing3; do mkdir -pv obj/$dir; done
Compiling : src/thing1/thing1.c
gcc -c -Wall -g -o obj/src/thing1/thing1.o src/thing1/thing1.c
Compiling : src/thing1/thing1.c
gcc -c -Wall -g -o obj/src/thing2/thing2.o src/thing1/thing1.c
Compiling : src/thing1/thing1.c
gcc -c -Wall -g -o obj/src/thing3/thing3.o src/thing1/thing1.c
ar -r -o thingy.a obj/src/thing1/thing1.o obj/src/thing2/thing2.o obj/src/thing3/thing3.o
ar: creating thingy.a
I'm very certain the problem is my use of $(SRC) in
$(OBJS) : $(SRC)
However, I just don't know what to do.
Anybody with MakeFu that could help?

Answer 1

Your $(OBJS) seems to be setup correctly, therefore the following should work (instead of $(OBJ) : $(SRC) target):
$(OBJDIR)/%.o : %.c
#echo Compiling : $<
$(C) -c $(CFLAGS) -o $# $<

Answer 2

You're right about the $(OBJS) rule being the problem.
Look at the variables: (SRC) is src/thing1/thing1.c src/thing2/thing2.c src/thing3/thing3.c, and $(OBJS) is obj/src/thing1/thing1.o obj/src/thing2/thing2.o obj/src/thing3/thing3.o. (Are you sure you want a src directory in obj/?) Now suppose you want to build obj/src/thing2/thing2.o using this rule:
$(OBJS) : $(SRC)
#echo Compiling : $<
$(C) -c $(CFLAGS) -o $# $<
The prerequisite field ($(SRC)) expands to "src/thing1/thing1.c src/thing2/thing2.c src/thing3/thing3.c", so $< expands to "src/thing1/thing1.c". Obviously what you want in this case is "src/thing2/thing2.c", so that's what the prerequisite field should be. What you need is something like a pattern rule or static pattern rule. The trick is that you don't know the paths ahead of time, and Make doesn't handle patterns well, so we have to be deft:
$(OBJS) : $(OBJDIR)/%.o : %.c
#echo Compiling : $<
$(C) -c $(CFLAGS) -o $# $<