I'm using this premade makefile. I tried adding heavyhitter.o and heavyhitter.h for those two files that I added to the application but I can't get it to work. I had added metadata_record.h and metadata_record.o without a problem and since I'm adding to the same area, I'm not sure why it worked before but isn't now.
CC = $(shell if test -f /opt/local/bin/gcc-mp-4.7; then \
echo gcc-mp-4.7; else echo gcc; fi)
CFLAGS = -std=gnu99 -g -W -Wall -O0 -gstabs -Iglib-2.0 -lglib-2.0
TESTS = $(patsubst %.c,%,$(sort $(wildcard test[0-9][0-9][0-9].c)))
%.o: %.c m61.h memory.h metadata_record.h heavyhitters.h
$(CC) $(CFLAGS) -o $# -c $
all: $(TESTS) hhtest
#echo "*** Run 'make check' or 'make check-all' to check your work."
test%: test%.o m61.o memory.o metadata_record.o heavyhitters.o
$(CC) $(CFLAGS) -o $# $^
test017: test017-help.o
hhtest: hhtest.o m61.o memory.o metadata_record.o heavyhitters.o
$(CC) $(CFLAGS) -o $# $^ -lm
check: $(TESTS) $(patsubst %,check-%,$(TESTS))
#echo "*** All tests succeeded!"
check-all: $(TESTS)
#x=true; for i in $(TESTS); do $(MAKE) check-$$i || x=false; done; \
if $$x; then echo "*** All tests succeeded!"; fi; $$x
check-test%: test%
#test -d out || mkdir out
#rm -f out/test$*.fail
#-sh -c "./$^ > out/test$*.output 2>&1" >/dev/null 2>&1; true
#perl compare.pl out/test$*.output test$*.c test$*
clean:
rm -f $(TESTS) hhtest *.o
rm -rf out
MALLOC_CHECK_=0
export MALLOC_CHECK_
.PRECIOUS: %.o
.PHONY: all clean check check-% prepare-check
It was actually supposed to be heavyhitter not heavyhitters
Related
I'm trying to compile my C project using clang (I'm on MacOS Monterry) and a Makefile, but I keep getting the same error from clang in the command line:
> make
gcc -c src/ji.c src/main.c -o src/ji.o
clang: error: cannot specify -o when generating multiple output files
make: *** [src/ji.o] Error 1
These are the only files I have in the project so far:
src/main.c
src/ji.c
include/ji.h
The Makefile looks like this:
cc = gcc
src = $(wildcard src/*.c)
obj = $(src:.c=.o)
exec = ji
$(exec): $(obj)
$(cc) -Iinclude $< -o build/$#
%.o: %.c
$(cc) -c $(src) -o $#
clean:
-rm src/*.o
-rm ji
From YouTube videos I've seen, this should be the ideal Makefile for the project but no matter what I change I get the error.
There are a few issues:
-Iinclude needs to be on the %.o: %.c rule command
In %.o: %.c, we don't want $(src) but rather $<
We want patsubst to get the .o list obj
The $(exec) target doesn't match the -o option
The clean doesn't match the placement of the executable
Here's a refactored version (e.g. one way to do this--there are others):
cc = gcc
src = $(wildcard src/*.c)
obj = $(patsubst %.c,%.o,$(src))
exec = build/ji
$(exec): $(obj)
mkdir -p build
$(cc) $^ -o $#
%.o: %.c
$(cc) -c $< -o $# -Iinclude
clean:
rm -f src/*.o
rm -fr build
Here's the output of make:
gcc -c src/ji.c -o src/ji.o -Iinclude
gcc -c src/main.c -o src/main.o -Iinclude
mkdir -p build
gcc src/ji.o src/main.o -o build/ji
Here's the output of make clean:
rm -f src/*.o
rm -fr build
I'm having trouble creating a pattern to apply to every file in a subdirectory
I have the following tree:
libft/
..makefile
..obj/
..bonus/
........bonusfile1.c
........bonusfile2.c
........bonusfile3.c
........[...etc...]
..mainfile1.c
..mainfile2.c
..mainfile3.c
..[...etc...]
I'm trying to compile the bonus/bonusfiles into the objects obj directory but no mater what I type I'm coming up short of my objective.
My makefile:
SRC_FILES= ft_atoi.c \
ft_bzero.c \
...
BONUS_FILES=ft_lstadd_back.c \
ft_lstadd_front.c \
...
NAME=libft.a
LIBSO=libft.so
CC=gcc
CFLAGS=-Wall -Wextra -Werror
BONUS_DIR=bonus/
OBJ_DIR=obj/
HDR_NAME=libft.h
BONUS_HDR=_bonus.h
SRC_PATH=$(addprefix $(SRC_DIR), $(SRC_FILES))
BONUS_PATH=$(addprefix $(BONUS_DIR), $(BONUS_FILES))
SRC_NAMES=${SRC_FILES:.c=.o}
BONUS_NAMES=${BONUS_FILES:.c=.o}
SRC_NAMES_O=$(addprefix $(OBJ_DIR), $(SRC_NAMES))
BONUS_NAMES_O=$(addprefix $(OBJ_DIR), $(BONUS_NAMES))
HDR= $(addprefix $(HDR_DIR),$(HDR_NAME))
all: $(NAME)
$(NAME): $(OBJ_DIR) $(SRC_NAMES)
ar -rc $# $(SRC_NAMES_O)
ranlib $#
$(OBJ_DIR):
mkdir $#
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $(OBJ_DIR)$#
bonus: $(BONUS_PATH)
ar -r $(NAME) $(BONUS_NAMES_O)
ranlib $#
$(BONUS_PATH): %.o: %.c
$(CC) $(CFLAGS) -c $< -o $(OBJ_DIR)$#
clean:
rm -rf $(OBJ_DIR)
rm -rf src/*.o
rm -rf *.o
sclean: clean
rm -rf $(NAME) $(LIBSO) a.out
fclean: clean
rm -f $(NAME)
re: fclean all
so:
$(CC) -nostartfiles -fPIC $(CFLAGS) $(SRC_FILES) $(BONUS_PATH)
gcc -nostartfiles -shared -o libft.so $(SRC_FILES) $(BONUS_PATH)
.PHONY: all clean fclean re so bonus
What I wanted to do was something similar to the %.o: %.c target but I can't. What am I doing wrong?
I've this problem:
when I try to compile my program, doing make command, I see the following error:
fatal error: json/json.h: No such file or directory
21 | #include <json/json.h>
I installed the json library throught the command sudo apt-get install -y libjson-c-dev and it was installed correctly. After that, I simply compiled the program adding -ljson-c to the makefile (I also tried with -lcjson and other names, none of them works). Here is my makefile:
ifndef MYDIR
MYDIR=../../
endif
TARGET=$(shell basename $(shell ls -1 *.c | head -n 1) .c)
TARGET2=$(shell basename $(shell ls -r -1 *.c | head -n 1) .c)
CFLAGS += -I$(MYDIR)/include
LDFLAGS += -L$(MYDIR)/lib
LIBS += -litsStatic -lpthread -lm -lrt -lconfig -lgps -ljson-c
all: $(TARGET)
$(TARGET): $(TARGET).c
$(CC) $(CFLAGS) -o $# $^ $(LDFLAGS) $(LIBS)
clean:
rm -f $(TARGET)
rm -f $(TARGET)/.o
.PHONY:clean
all: $(TARGET2)
$(TARGET2): $(TARGET2).c
$(CC) $(CFLAGS) -o $# $^ $(LDFLAGS) $(LIBS)
clean:
rm -f $(TARGET2)
rm -f $(TARGET2)/.o
.PHONY:clean
Where is the problem? Thank you for your help!
I have a beginner's question about a Makefile. I have a very simple makefile containing:
SHELL = /bin/sh
CC = gcc
CFLAGS = -lm -std=c99 -g -o0
EXEC = test
BUILDDIR = build
OBJDIR = obj
SOURCES = $(shell cat sources.list)
DEPS = $(shell cat headers.list)
OBJ = $(SOURCES:.c=.o)
OBJECTS = $(patsubst %,$(OBJDIR)/%,$(OBJ))
all: $(OBJECTS)
$(CC) $(CFLAGS) $(OBJECTS) -o $(BUILDDIR)/$(EXEC)
$(OBJDIR)/%.o: %.c $(DEPS)
$(CC) -c $< -o $#
clean:
rm -f $(BUILDDIR)/$(EXEC) $(OBJDIR)/*.o
My Problem is, if I try to use this Makefile to compile, it returns the error message:
there is no rule for the target obj/Name.o
What am I doing wrong?
After the first few comments and further research I got to this working Version, but it does not create the object files in the obj folder, so it is not what I aim for
SHELL = /bin/sh
CC = gcc
CFLAGS = -lm -std=c99 -g -o0
EXEC = test
BUILDDIR = build
OBJDIR = obj
SOURCES = $(shell cat sources.list)
DEPS = $(shell cat headers.list)
OBJ = $(SOURCES:.c=.o)
OBJECTS = $(patsubst %,$(OBJDIR)/%,$(OBJ))
all: $(BUILDDIR)/$(EXEC)
$(BUILDDIR)/$(EXEC): $(OBJ)
$(CC) $(CFLAGS) $(OBJ) -o $(BUILDDIR)/$(EXEC)
%.o: %.c $(DEPS)
$(CC) -c $< -o $#
clean:
rm -f $(BUILDDIR)/$(EXEC) $(OBJDIR)/*.o
Are all the files in headers.list present at the right place ?
By the way, this is not a good way to handle dependencies on headers. You should take a look at -MP and -MDD and other options of your preprocessor to generate dependencies.
A classical makefile which should do what you need:
SHELL=/bin/bash
CC=gcc
CFLAGS=-std=c99 -g -o0
LDFLAGS=-lm
EXEC=test
BUILDDIR=build/
OBJDIR=obj/
SOURCES=$(shell cat sources.list)
OBJECTS=$(patsubst %.c,$(OBJDIR)%.o,$(notdir $(SOURCES)))
vpath %.c $(sort $(dir $(SOURCES)))
.PHONY:all mrproper clean depends
all:$(BUILDDIR)$(EXEC)
$(BUILDDIR)$(EXEC):$(OBJECTS)|$(BUILDDIR)
$(CC) $(CFLAGS) $^ -o $# $(LDFLAGS)
$(OBJDIR)%.o:%.c|$(OBJDIR)
$(CC) -c $< -o $#
$(BUILDDIR) $(OBJDIR):
mkdir $#
mrproper:clean
rm -f $(BUILDDIR)$(EXEC)
clean:
rm -f $(OBJECTS)
depends:
#rm -f dependencies.mk
#for i in $(SOURCES); do $(CC) -MM $$i -MT $(OBJDIR)`basename $$i | sed s:.c$$:.o:` >> dependencies.mk; done
include $(wildcard dependencies.mk)
If something is not clear, let me know.
Usage:
make depends
make
I have an makefile but doesn't work. The error in terminal is this: cc -shared -o build/liblcthw.so src/lcthw/list.o
/usr/bin/ld: src/lcthw/list.o: relocation R_X86_64_32 against `.rodata' can not be used when making a shared object; recompile with -fPIC
src/lcthw/list.o: error adding symbols: Bad value
I need help to put the gcc comand gcc -shared -o target.so -fPIC target.c, i don't how to put the target.c instead list.o
This is the makefile:
CFLAGS=-g -O2 -Wall -Wextra -Isrc -rdynamic -DNDEBUG $(OPTFLAGS)
LIBS=-ldl $(OPTLIBS)
PREFIX?=/usr/local
SOURCES=$(wildcard src/**/*.c src/*.c)
OBJECTS=$(patsubst %.c,%.o,$(SOURCES))
TEST_SRC=$(wildcard tests/*_tests.c)
TESTS=$(patsubst %.c,%,$(TEST_SRC))
TARGET=build/liblcthw.a
SO_TARGET=$(patsubst %.a,%.so,$(TARGET))
# The Target Build
all: $(TARGET) $(SO_TARGET) tests
dev: CFLAGS=-g -Wall -Isrc -Wall -Wextra $(OPTFLAGS)
dev: all
$(TARGET): CFLAGS += -fPIC
$(TARGET): build $(OBJECTS)
ar rcs $# $(OBJECTS)
ranlib $#
$(SO_TARGET): $(TARGET) $(OBJECTS)
$(CC) -shared -o $# $(OBJECTS)
build:
#mkdir -p build
#mkdir -p bin
# The Unit Tests
.PHONY: tests
tests: CFLAGS += $(TARGET)
tests: $(TESTS)
sh ./tests/runtests.sh
valgrind:
VALGRIND="valgrind --log-file=/tmp/valgrind-%p.log" $(MAKE)
# The Cleaner
clean:
rm -rf build $(OBJECTS) $(TESTS)
rm -f tests/tests.log
find . -name "*.gc*" -exec rm {} \;
rm -rf `find . -name "*.dSYM" -print`
# The Install
install: all
install -d $(DESTDIR)/$(PREFIX)/lib/
install $(TARGET) $(DESTDIR)/$(PREFIX)/lib/
# The Checker
BADFUNCS='[^_.>a-zA-Z0-9](str(n?cpy|n?cat|xfrm|n?dup|str|pbrk|tok|_)|stpn?cpy|a?sn?printf|byte_)'
check:
#echo Files with potentially dangerous functions.
#egrep $(BADFUNCS) $(SOURCES) || true
Your objects for liblcthw.a are built with -fPIC. Objects for liblcthw.so are not built with this setting.
Try changing rule:
$(SO_TARGET): $(TARGET) $(OBJECTS)
$(CC) -shared -o $# $(OBJECTS)
to:
$(SO_TARGET): $(TARGET)
$(CC) -shared -o $# $^
Since the required objects are already in liblcthw.a.
Or, alternatively:
$(SO_TARGET): CFLAGS += -fPIC
$(SO_TARGET): $(OBJECTS)
$(CC) -shared -o $# $(OBJECTS)