I am compiling a Kernel Module in Linux 3.2.6.
I have module.h in /usr/src/linux/include/linux, except when I go to compile it with my makefile, it tells me module.h can not be found.
In my makefile, I also have KDIR set to the location of the modules.
How can I fix this?
My make file is:
MODCFLAGS := -Wall -DMODULE -D__KERNEL__ -DLINUX
obj-m := hello.o
KDIR := /usr/src/linux/include/
PWD := `pwd`
default:
make -C $(KDIR) M=$(PWD) modules
Related
To start building a block-drive (it is called "out of tree"?) module, I'm trying to compile just some headers from Linux.
Edit: Deleted .c file and renamed .h file to .c, but the same 1 error persists.
BlockVRAM.c:
#include <linux/module.h>
Makefile:
BINARY := BlockVRAM
KERNEL := /lib/modules/$(shell uname -r)/build
ARCH := x86
C_FLAGS := -D__KERNEL__ -Wall -I/usr/src/linux-headers-5.4.0-66-generic/include/ -I/usr/src/linux-headers-5.4.0-66-generic/arch/x86/include
KMOD_DIR := $(shell pwd)
TARGET_PATH := /lib/modules/$(shell uname -r)/kernel/drivers/char
OBJECTS := BlockVRAM.o
CC += $(C_FLAGS)
obj-m := $(BINARY).o
$(BINARY)-y := $(OBJECTS)
$(BINARY).ko:
make ARCH=x86 -C $(KERNEL) M=$(KMOD_DIR) modules
install:
cp $(BINARY).ko $(TARGET_PATH)
depmod -a
clean:
rm -f *.ko
rm -f *.o
There is only 1 error it is returning:
In file included from /usr/src/linux-headers-5.4.0-66-generic/include/linux/time64.h:10:0,
from /usr/src/linux-headers-5.4.0-66-generic/include/linux/restart_block.h:10,
from /usr/src/linux-headers-5.4.0-66-generic/include/linux/thread_info.h:13,
from /usr/src/linux-headers-5.4.0-66-generic/arch/x86/include/asm/preempt.h:7,
from /usr/src/linux-headers-5.4.0-66-generic/include/linux/preempt.h:78,
from /usr/src/linux-headers-5.4.0-66-generic/include/linux/spinlock.h:51,
from /usr/src/linux-headers-5.4.0-66-generic/include/linux/seqlock.h:36,
from /usr/src/linux-headers-5.4.0-66-generic/include/linux/time.h:6,
from /usr/src/linux-headers-5.4.0-66-generic/include/linux/stat.h:19,
from /usr/src/linux-headers-5.4.0-66-generic/include/linux/module.h:10,
from BlockVRAM.h:12,
from BlockVRAM.c:11:
/usr/src/linux-headers-5.4.0-66-generic/include/uapi/linux/time.h:6:10: fatal error: linux/time_types.h: No such file or directory
#include <linux/time_types.h>
^~~~~~~~~~~~~~~~~~~~
compilation terminated.
<builtin>: recipe for target 'BlockVRAM' failed
make: *** [BlockVRAM] Error 1
I tried to include that folder as an include flag but it only caused re-definition errors. I don't know what I'm doing wrong. OS is Ubuntu 18.04 LTS.
Using Makefile as this:
sudo make BlockVRAM
in same folder of source file.
I started from here but there were a lot of errors until I added those two include directory flags in Makefile.
I am trying to compile a kernel module that has two .c files. My Makefile is the following
module-y: dummy.o library.o
obj-m += module.o
default:
make -C /lib/modules/`uname -r`/build M=$(PWD) modules
When I run this I get
cc -c -o dummy.o dummy.c
dummy.c:3:24: fatal error: linux/init.h: No such file or directory
It seems the Makefile doesn't know where to find the headers now.
I have tried using CFLAGS to add include directories, but there are so many of them that it becomes tedious and hard to do (haven't managed to make it work).
I would like to generate these two .o files using the include directories that are (magically) used when using a single .c file. Everything works fine in that case.
How to fix the include directories when using two source files?
I wrote the Makefile like the following, and it worked:
ifneq ($(KERNELRELEASE),)
# kbuild part of makefile
obj-m := module.o
module-y := library.o dummy.o
else
# normal makefile
KDIR ?= /lib/modules/`uname -r`/build
default:
$(MAKE) -C $(KDIR) M=$$PWD modules
endif
I want to write a Kernel Module and now I have written some files: a.c, b.c, b.h and d.h.
a.c includes b.h and d.h and b.h includes d.h too.
I wrote a Makefile like this:
ifneq ($(KERNELRELEASE),)
mymodule-objs :=a.c b.c
obj-m += a.o b.o
else
PWD := $(shell pwd)
KVER := $(shell uname -r)
KDIR := /lib/modules/$(KVER)/build
all:
rm -rf *.o *.mod.c *.symvers *order *.markers *.cmd *-
$(MAKE) -C $(KDIR) M=$(PWD)
clean:
rm -rf *.o *.mod.c *.symvers *order *.markers *.cmd *-
endif
But it doesn't work, how should I write a correct Makefile? I want to get a file name x.ko in end and.
After I use the 'make' command, and I use 'insmod' is give me a message:
insmod: ERROR: could not insert module a.ko: Unknown symbol in module
By the way I use Ubuntu 14.10. The kernel is 3.16.0-37-generic
obj-m += a.o b.o
will create two modules, a.ko and b.ko
if you want to create a single module out of both (which I suppose you do because of the line with mymodule-objs), replace that line with
obj-m += mymodule.o
mymodule.o will be built according to mymodule-objs and then turned into mymodule.ko using modpost.
And as said before, you're missing modules in your $(MAKE) line
Try modelling your Makefile after this?
https://unix.stackexchange.com/questions/122095/understanding-a-make-file-for-making-ko-files
You might not need mymodule-objs := a.c b.c. And I think you're missing modules after the $(MAKE) line
I am trying to compile my kernel module.
The .c file name is file1.c, but I need the .ko file name to be mod1.ko.
How can I do that?
My current makefile:
obj-m := mod1.o
KDIR :=/lib/modules/$(shell uname -r)/build
PDW := $(shell pwd)
all:
$(MAKE) -C $(KDIR) M=$(PDW) modules
clean:
$(MAKE) -C $(KDIR) M=$(PDW) clean
You should change your first line to something like this:
obj-m += module_name.o
module_name-y := file1.o
Where module_name is the module file name (in this example the output will be module_name.ko) and it will be build from file1.c. You can add more than one source file to the 2nd line, so it could be:
module_name-y := file1.o file2.o file3.o
In this case module_name.ko will be build from file1.c, file2.c and file3.c.
You should read this document if you want to fully understand Linux kernel makefiles. Your problem is described somewhere around line 190.
The solution looks like this:
obj-m += mod1.o
mod1-objs := file1.o
KBUILD_CPPFLAGS += -I$(PWD)/
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Is it possible to build a kernel module from several source files which one of them has the same name as the module?
For example:
I want to build "mymodule.ko" with the following source files:
mymodule.c
mymodule_func.c
This makefile doesn't work:
#Makefile
obj-m += mymodule.o
mymodule-objs := mymodule.o mymodule_func.o
thanks
I found a solution, I placed my source file in a sub folder:
Makefile
src/mymodule.c
src/mymodule_func.c
#Makefile
obj-m += mymodule.o
mymodule-objs := ./src/mymodule.o ./src/mymodule_func.o
all:
make -C $(KERNEL_PATH) M=$(PWD) modules
clean:
make -C $(KERNEL_PATH) M=$(PWD) clean
Proper way to fix in kernel make file would be as:
#
obj-m+= my_module.o
#append other source files except my_module.c which would be include by default
my_module-objs+= src1.o src2.o
As per my understanding it is not possible to have the module name and the source name to be the same. It would be better to provide module name as module.o and use the Makefile for compiling loadable kernel module as shown below,
Makefile
# If KERNELRELEASE is defined, we've been invoked from the
# kernel build system and can use its language.
ifneq ($(KERNELRELEASE),)
**obj-m := module.o
module-objs := mymodule.o mymodule_func.o**
# Otherwise we were called directly from the command
# line; invoke the kernel build system.
EXTRA_CFLAGS += -DDEBUG
else
KERNELDIR := /lib/modules/$(shell uname -r)/build
PWD := $(shell pwd)
default:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
endif
clean:
$(MAKE) -C $(KERNELDIR) SUBDIRS=$(PWD) clean
You can use TARGET to name your .ko file as I did in this example:
TARGET = can
KDIR = /lib/modules/3.1.10-1.16-desktop/build
PWD := $(shell pwd)
obj-m += $(TARGET).o
can-objs := can_core.o can_open.o can_select.o can_sysctl.o can_write.o \
can_close.o can_ioctl.o can_read.o can_util.o \
can_debug.o can_error.o \
can_async.o can_sim.o
default:
make -C $(KDIR) M=$(PWD) modules
So after the build I ended with a bunch of object files and can.ko
Another solution is create symlink to the file, say:
mymodule.c: ln -sf mymodule.c _mymodule.c
Now, use _mymodule.o as the object name:
mymodule-objs := _mymodule.o
If anyone has stumbled upon this issue while working with Xilinx SoCs and petalinux, note the generated .bb (bitbake) file. Apart from specifying object files in the Makefile:
modulename-objs+= src1.o src2.o
all files (including headers) must be listed in the modulename.bb file's SRC_URI variable.